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CURSUL 2: INTRODUCTION (2)

2

INTRODUCTION

• Integrated circuits: many transistors on one chip.

• Very Large Scale Integration (VLSI): bucketloads!

• Complementary Metal Oxide Semiconductor• Fast, cheap, low power transistors

• Today: How to build your own simple CMOS chip• CMOS transistors• Building logic gates from transistors• Transistor layout and fabrication

• Rest of the course: How to build a good CMOS chip

3

SILICON LATTICE

• Transistors are built on a silicon substrate• Silicon is a Group IV material• Forms crystal lattice with bonds to four neighbors

Si SiSi

Si SiSi

Si SiSi

4

DOPANTS

• Silicon is a semiconductor• Pure silicon has no free carriers and conducts poorly• Adding dopants increases the conductivity• Group V: extra electron (n-type) Arsenic• Group III: missing electron, called hole (p-type) Boron

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-

5

P-N JUNCTIONS

• A junction between p-type and n-type semiconductor forms a diode.

• Current flows only in one direction

p-type n-type

anode cathode

6

NMOS TRANSISTOR

• Four terminals: gate, source, drain, body

• Gate – oxide – body stack looks like a capacitor• Gate and body are conductors• SiO2 (oxide) is a very good insulator• Called metal – oxide – semiconductor (MOS) capacitor• Even though gate is no longer made of metal*

* Metal gates are returning today!

7

NMOS OPERATION

• Body is usually tied to ground (0 V)

• When the gate is at a low voltage:• P-type body is at low voltage

• Source-body and drain-body diodes are OFF

• No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S

8

NMOS OPERATION CONT.

• When the gate is at a high voltage:• Positive charge on gate of MOS capacitor

• Negative charge attracted to body

• Inverts a channel under gate to n-type

• Now current can flow through n-type silicon from source through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S

9

PMOS TRANSISTOR

• Similar, but doping and voltages reversed• Body tied to high voltage (VDD)

• Gate low: transistor ON

• Gate high: transistor OFF

• Bubble indicates inverted behavior

10

POWER SUPPLY VOLTAGE

• GND = 0 V

• In 1980’s, VDD = 5V

• VDD has decreased in modern processes• High VDD would damage modern tiny transistors

• Lower VDD saves power

• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

11

TRANSISTORS AS SWITCHES

• We can view MOS transistors as electrically controlled switches• Voltage at gate controls path from source to drain

gs

d

g = 0

s

d

g = 1

s

d

gs

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF

1: Circuits & Layout12

COMPLEMENTARY CMOS

• Complementary CMOS logic gates• nMOS pull-down network

• pMOS pull-up network

• a.k.a. static CMOS

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetworkPull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

0: Introduction13

0

CMOS INVERTER

A Y

0 1

1 0

A Y

OFF

ON 1

ON

OFF


SERIES AND PARALLEL

• nMOS: 1 = ON

• pMOS: 0 = ON

• Series: both must be ON

• Parallel: either can be ON

(a)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

OFF OFF OFF ON

(b)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

ON OFF OFF OFF

(c)

a

b

a

b

g1 g2 0 0

OFF ON ON ON

(d) ON ON ON OFF

a

b

0

a

b

1

a

b

11 0 1

a

b

0 0

a

b

0

a

b

1

a

b

11 0 1

a

b

g1 g2

0: Introduction15

CMOS NAND GATEA B Y

0 0 1

0 1 1

1 0 1

1 1 0

OFFOFF

ON

ON

1

1

OFFON

OFF

ON

0

1

ON OFF

ON

OFF

1

0

ON ON

OFF

OFF

0

0A

B

Y

16

CMOS NOR GATEA B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

BY

17

3-INPUT NAND GATE

• Y pulls low if ALL inputs are 1

• Y pulls high if ANY input is 0 AB

Y

C

COMPOUND GATES

• Compound gates can do any inverting function

• Ex:

A

B

C

D

A

B

C

D

A B C DA B

C D

B

D

YA

CA

C

A

B

C

D

B

D

Y

(a)

(c)

(e)

(b)

(d)

(f)

Y (A · B) (C · D) (AND-AND OR INV AOI22)

SIGNAL STRENGTH

• Strength of signal• How close it approximates ideal voltage source

• VDD and GND rails are strongest 1 and 0

• nMOS pass strong 0• But degraded or weak 1

• pMOS pass strong 1• But degraded or weak 0

• Thus nMOS are best for pull-down network

PASS TRANSISTORS

• Transistors can be used as switches


TRANSMISSION GATES

• Pass transistors produce degraded outputs

• Transmission gates pass both 0 and 1 well

g = 0, gb = 1a b

g = 1, gb = 0a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a bg

gb

a bg

gb

a bg

gb

g = 1, gb = 0

g = 1, gb = 0

TRISTATES

• Tristate buffer produces Z when not enabled

EN A Y0 0 Z0 1 Z1 0 01 1 1

A Y

EN

A Y

EN

EN

NONRESTORING TRISTATE

• Transmission gate acts as tristate buffer• Only two transistors

• But nonrestoring

• Noise on A is passed on to Y

A Y

EN

EN

MULTIPLEXERS

• 2:1 multiplexer chooses between two inputs

S D1 D0 Y

0 X 0 0

0 X 1 1

1 0 X 0

1 1 X 1

0

1

S

D0

D1Y

4:1 MULTIPLEXER

• 4:1 mux chooses one of 4 inputs using two selects• Two levels of 2:1 muxes

• Or four tristates

S0

D0

D1

0

1

0

1

0

1Y

S1

D2

D3

D0

D1

D2

D3

Y

S1S0 S1S0 S1S0 S1S0

D LATCH

• When CLK = 1, latch is transparent• D flows through to Q like a buffer

• When CLK = 0, the latch is opaque• Q holds its old value independent of D

• a.k.a. transparent latch or level-sensitive latchCLK

D Q

Latc

h D

CLK

Q

D LATCH DESIGN

• Multiplexer chooses D or old Q

1

0

D

CLK

QCLK

CLKCLK

CLK

DQ Q

Q

D LATCH OPERATION

CLK = 1

D Q

Q

CLK = 0

D Q

Q

D

CLK

Q

D FLIP-FLOP DESIGN

• Built from master and slave D latches

QMCLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latc

h

Latc

h

D QQM

CLK

CLK

D FLIP-FLOP OPERATION

CLK = 1

D

CLK = 0

Q

D

QM

QMQ

D

CLK

Q

0: Introduction31

CMOS FABRICATION

• CMOS transistors are fabricated on silicon wafer

• Lithography process similar to printing press

• On each step, different materials are deposited or etched

• Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

0: Introduction32

INVERTER CROSS-SECTION

• Typically use p-type substrate for nMOS transistors

• Requires n-well for body of pMOS transistors

0: Introduction33

WELL AND SUBSTRATE TAPS

• Substrate must be tied to GND and n-well to VDD

• Metal to lightly-doped semiconductor forms poor connection called ShottkyDiode

• Use heavily doped well and substrate contacts / taps

0: Introduction34

INVERTER MASK SET

• Transistors and wires are defined by masks

• Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor

0: Introduction35

DETAILED MASK VIEWS

• Six masks• n-well

• Polysilicon

• n+ diffusion

• p+ diffusion

• Contact

• Metal

FABRICATION

• Chips are built in huge factories called fabs

• Contain clean rooms as large as football fields

Courtesy of InternationalBusiness Machines Corporation. Unauthorized use not permitted.

INTEGRATED CIRCUITS ON WAFERS

The Ingot is cut into individual silicon discs called wafers

In this picture you can see how one big crystal is grown from the purified silicon melt. The resulting mono crystal is called Ingot.

COST OF AN IC• The total cost of a product can be separated into

two components: the recurring expenses (variable cost) and the non-recurring expenses (fixed cost).

• Fixed cost; man-power, company’s R&D, manufacturing equipment, marketing, sales, building infrastructures,…

• Variable cost; directly attributes to a manufactures product and is proportional to the product volume.

FABRICATION STEPS

• Start with blank wafer

• Build inverter from the bottom up

• First step will be to form the n-well• Cover wafer with protective layer of SiO2 (oxide)

• Remove layer where n-well should be built

• Implant or diffuse n dopants into exposed wafer

• Strip off SiO2

p substrate

0: Introduction40

OXIDATION

• Grow SiO2 on top of Si wafer• 900 – 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2

0: Introduction41

PHOTORESIST

• Spin on photoresist• Photoresist is a light-sensitive organic polymer

• Softens where exposed to light

p substrate

SiO2

Photoresist

0: Introduction42

LITHOGRAPHY

• Expose photoresist through n-well mask

• Strip off exposed photoresist

p substrate

SiO2

Photoresist

0: Introduction43

ETCH

• Etch oxide with “Acid fluorhidric”• Seeps through skin and eats bone; nasty stuff!!!

• Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist

0: Introduction44

STRIP PHOTORESIST

• Strip off remaining photoresist• Use mixture of acids called piranah etch

• Necessary so resist doesn’t melt in next step

p substrate

SiO2

N-WELL• n-well is formed with diffusion or ion implantation

• Diffusion• Place wafer in furnace with arsenic gas

• Heat until As atoms diffuse into exposed Si

• Ion Implanatation• Blast wafer with beam of As ions

• Ions blocked by SiO2, only enter exposed Si

n well

SiO2

STRIP OXIDE

• Strip off the remaining oxide using HF

• Back to bare wafer with n-well

• Subsequent steps involve similar series of steps

p substraten well

POLYSILICON

• Deposit very thin layer of gate oxide• < 20 Å (6-7 atomic layers)

• Chemical Vapor Deposition (CVD) of silicon layer• Place wafer in furnace with Silane gas (SiH4)

• Forms many small crystals called polysilicon

• Heavily doped to be good conductor

POLYSILICON PATTERNING

• Use same lithography process to pattern polysilicon

Polysilicon

SELF-ALIGNED PROCESS

• Use oxide and masking to expose where n+ dopants should be diffused or implanted

• N-diffusion forms nMOS source, drain, and n-well contact

N-DIFFUSION• Pattern oxide and form n+ regions

• Self-aligned process where gate blocks diffusion

• Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

p substraten well

N-DIFFUSION CONT.

• Historically dopants were diffused

• Usually ion implantation today

• But regions are still called diffusion

N-DIFFUSION CONT.

• Strip off oxide to complete patterning step

P-DIFFUSION

• Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

CONTACTS

• Now we need to wire together the devices

• Cover chip with thick field oxide

• Etch oxide where contact cuts are needed

Contact

METALIZATION

• Sputter on aluminum over whole wafer

• Pattern to remove excess metal, leaving wires

M etal

LAYOUT

• Chips are specified with set of masks

• Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)

• Feature size f = distance between source and drain• Set by minimum width of polysilicon

• Feature size improves 30% every 3 years or so

• Normalize for feature size when describing design rules

• Express rules in terms of = f/2• E.g. = 0.3 m in 0.6 m process

SIMPLIFIED DESIGN RULES

• Conservative rules to get you started

0: Introduction58

INVERTER LAYOUT• Transistor dimensions specified as Width / Length

• Minimum size is 4 / 2sometimes called 1 unit

• In f = 0.6 m process, this is 1.2 m wide, 0.6 m long

SUMMARY

• MOS transistors are stacks of gate, oxide, silicon

• Act as electrically controlled switches

• Build logic gates out of switches

• Draw masks to specify layout of transistors

• Now you know everything necessary to start designing schematics and layout for a simple chip!

ABOUT THESE NOTES

• CMOS VLSI Design: A circuit and system perspective, Weste&Harris. http://cmosvlsi.com/

• Lecture notes © 2011 David Money Harris

• These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.

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