Performed by:Volokitin VladimirTsesis FelixInstructor: Mony Orbah

מהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

) ( סופי” פרויקט סיכום ח דוSubject:

High Pass Filter on SOPC

) / שנה ) קיץ חורף סמסטר1

Abstractמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

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Digital Signal Processing is an important aspect of the most digital systems which use physical data as their input. This digital data is being filtered after the transformation. In this project we implement the High Pass digital Filter using Matlab and Xilinx –System Generator as software platform and Virtex II Pro board as a Hardware platform. The project was Designed and partly tested by Xilinx Toolbox in Matlab and then implemented on hardware and tested on Virtex II Pro FPGA board using Matlab as an interface and debugging tool.This way of the design flow is much easier due to simple interfaceand good integration between the software and the hardware.

System descriptionמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

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•We designed the HPF using the Matlab Simulink and System Generator of the Xilinx.

•Next step – Hardware in the loop – simulation through the FPGA

Specificationמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

• Hardware

• Software

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Xilinx’s Virtex II Pro platform design

Matlab – SimulinkSystem Generator - Xilinx

System Block Diagramמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

5

In2Out2

section5

In2Out2

section4

In2Out2

section3

In2Out2

section2

In2Out1

section1

Uniform RandomNumber

d qz-1

Register6

d qz-1

Register5

d qz-1

Register4

d qz-1

Register3

d qz-1

Register2

d qz-1

Register1

Out

Gateway Out

In

Gateway In

Input Output

Filter

B-FFT

FPGA Spectrum

FDATool

FDATool1Sy stemGenerator

JTAGCo-sim

Gateway 100

Gateway 10

Gateway 11

Gateway 12

Gateway 13

Gateway 14

Gateway 15

Gateway 16

Gateway 17

Gateway 18

Gateway 19

Gateway 1

Gateway 20

Gateway 2

Gateway 3

Gateway 4

Gateway 5

Gateway 6

Gateway 7

Gateway 8

Gateway 9

Gateway In22

Gateway Out

fi l ter_our_coff2_13_10hwcosim

Uniform RandomNumber1

B-FFT

SpectrumScope1

ResourceEstimator

Out

Gateway Out2

In

Gateway 43

In

Gateway 41

In

Gateway 40

In

Gateway 39

In

Gateway 38

In

Gateway 37

In

Gateway 36

In

Gateway 35

In

Gateway 34

In

Gateway 33

In

Gateway 32

In

Gateway 31

In

Gateway 30

In

Gateway 29

In

Gateway 28

In

Gateway 27

In

Gateway 26

In

Gateway 25

In

Gateway 24

In

Gateway 23

In

Gateway 22

In

Gateway 21

Input Output

Filter1

FDATool

FDATool1

-C-

Constant81

-C-

Constant8

1

Constant32

-C-

Constant31

-C-

Constant30

G(5)

Constant29

-C-

Constant28

-C-

Constant27

-C-

Constant26

G(4)

Constant25

-C-

Constant24

-C-

Constant23

G(3)

Constant22

-C-

Constant21

-C-

Constant22

-C-

Constant21

G(1)

Constant2

-C-

Constant19

-C-

Constant111

G(2)

Constant11

-C-

Constan1

Sy stemGenerator

System Block Diagramמהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

FPGA Block Diagram

מהירות ספרתיות למערכות High speed digital systems laboratoryהמעבדה

6

ProcessorPLB

Interface

Data Bus

ADDR Bus

PLB CommandSet

CoefficientsFIFO

IN

Address/Enable

Generator

ADDR Bus

PLB Command

Set

Addr

En

Data In

Coefficients

FILTER

Data In

Enable

Coefficients

FIFOOut

Data Out

En

Addr

PLBInterfa

ce

Data out

Data Out

ChipScope