【指令篇】 第 1 章:plc 階梯圖程式基本原理及簡碼指令 · pdf file1-2...

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1-1 1 章: PLC 階梯圖程式基本原理及簡碼指令之轉譯法則 本章將介紹 PLC 階梯圖程式之基本原理,以及將階梯圖程式轉換成簡碼指令 Mnemonic )之轉譯法則。 1.1 階梯圖工作原理 階梯圖為二次世界大戰期間所發展出來之自動控制圖形語言,是歷史最久、使用最廣之 自動控制語言,最初只有 A (常開)接點、 B (常閉)接點、輸出線圈、計時器、計數器等 基 本 機 構 元 件( 今 日 仍 在 使 用 之 配 電 盤 即 是 ),直 到 微 電 腦 PLC 出現後,階梯圖之元件(語 言)除上述元件外尚增加了諸如微分接點、保持線圈等元件(請參閱 1-6 頁之元件類別)以 及傳統配電盤無法達成之應用指令。 無論傳統階梯圖或 PLC 階梯圖其工作原理均相同,只是在符號表示上傳統階梯圖以較 接近實體之符號表示,而 PLC 則採用較簡明且易於電腦或報表上表示之符號表示。在階梯 圖邏輯方面可分為組合邏輯和順序邏輯兩種,茲分述如下: 1.1.1 組合邏輯 組合邏輯之階梯圖係單純地將單一或一個以上之輸入元件組合(串、並聯等)後再將結 果送到輸出元件(線圈、計時/計數器或應用指令等)之回路結構。 回路 1 回路 2 回路 3 【指令篇】 X0 Y0 X1 Y1 X2 X4 X2 X3 AC110V NC(A) NC(B) NC NO NO

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  • 1-1

    1 PLC

    PLC Mnemonic

    1.1

    A B PLC 1-6

    PLC PLC

    1.1.1

    1

    2

    3

    NO

    NC

    X3

    NC(B)

    X2

    NO(A)

    X1

    NO

    X4 Y2

    Y1

    X0

    AC110V

    Y0

    X0 Y0

    X1 Y1

    X2 X4 X2

    X3

    A C 11 0 V

    N C ( A )

    N C ( B )

    N C

    N O

    N O

  • 1-2

    PLC 1 NO Normally Open A OFF ON 2 NC Normally Close B

    3 Y2 X2 X3 X4

    PLC

    1

    2

    3

    X0

    X1

    X2

    X3

    X4

    Y0

    Y1

    Y2

    1

    2

    3

    X0

    X1

    X2

    X3

    X4

    Y0

    Y1

    Y2

    1.1.2

    1

    2

    AC110V

    Y3X5

    NO NC

    X6

    X5 X6

    N O NC

    Y3

    AC110 V

  • 1-3

    PLC

    X5

    Y3

    X6 Y3 X5

    Y3

    X6 Y3

    X6 ON X5 OFF 1 2 A ON 1 2 X5 1 2 ON X5 OFF 1

    X5 (NO)

    X6 (NC)

    X5 X6

    PLC Sequencer A B 5

    1.2 PLC

    PLC PLC CPU

    CPU /

    PLC PLC PLC PLC ASIC IC PLC FBs-PLC 1K step 0.33ms PLC

  • 1-4

    ( )

    X0

    Y0

    M100

    X100

    X1

    X3

    M505

    X10

    Y126

    Y0

    Y1

    Firststep

    Last step

    Input processing (Reading thestatus of all external input terminals)

    Output processing (Output the resultingsignals to external output terminals)

    PLC X0 X1 X4 X6 Y0 ON PLC PLC CPU a X3 OFF CPU OFF a X4 b ON PLC CPU Y0 OFF

    X2

    X5

    X0

    X3

    X1

    X4

    X6

    a b

    Y0

    X1 Y0X2 X0

    X3 X5X4

    X6

    a b

  • 1-5

    1.3

    Y4

    X11

    X14

    M6Y0

    X16

    X10

    X12

    M1 X20

    X1X0

    X7 X10

    X2

    X9

    X3 X4 X5 X6

    /

    Y4

    Y5

    /

    Y2

    Y0

    Serial blockParallel blockNodeElement

    Origin line

    Network 1

    Network 2

    Network 3

    Branch

    ( FBs PLC 22 16 )

    8 11 88

    Contact

    ON OFF X FBs PLC A B 6

    Relay

    Coil Contact

    Y0

    COIL

    Y0

    Y0

    Y0

    Y0

    A

    B

    TU

    TD

    X5X4 X6 Y0

    Y2

    X3X2

    X9X10

    X1

    X7

    Y4

    X10 X11

    1

    X0

    Y5

    Y4

    M6

    M1

    Y0

    X12

    X20

    X16

    2

    3

    X14

  • 1-6

    OUT Y0 1 ON A 1 B 0 TU ON TD 0 Y0 OFF A 0 B 1 TU 0 TD ON A B TU TD 4

    FBs-PLC Y M S TR Y

    Origin

    Element OP Code Operand

    X100 Y15

    FBs PLC 9

    A

    (ORG LD AND OR) XY

    M S T C 2.2

    B

    (ORG LD AND OR)NOT

    (ORG LD AND OR)TU XY

    M S

    (ORG LD AND OR)TD

    (ORG LD AND OR)OPEN

    (ORG LD AND OR)SHORT

    OUT

    YMS

    OUT NOT

    Y

    L OUT L Y

    X Y M S T C 2.2 4.2

    OUT TRn LD TRn FOn 1.6 TR 5.1.4 FO

  • 1-7

    Node FBs-PLC 4.3

    Block

    1.5

    Branch

    21

    1 2

  • 1-8

    Network

    1 3

    1.4 (WinProladder )

    FBs-PLC WinProladder FP-08 FP-08 1.6 Mnemonic

    ORG ORG 5.1.1

    X0

    X2

    X3

    X1

    X4

    X5

    ORG X 0AND X 1LD X 2OR X 3AND X 4ORLD AND X 5

    LD

    1

    X0

    M0

    X1

    ORG M 0LD X 0AND X 1ORLD

    2

    X0

    M0

    X1

    M1Y0

    AND Y 0LD M 0AND M 1LD X 0AND X 1ORLD

    1 AND

    X0

    Y0

    AND X 0 ORLD AND Y 0

  • 1-9

    2 OUT TR AND

    OUT TR0 LD TR0

    Y0

    X0 Y1M0

    AND M 0 OUT TR 0 AND X 0 OUT Y 1 LD TR 0 AND Y 0

    AND

    X0 X1

    ORG X 0AND X 1

    OR

    1 X0 X2

    X1

    ORG X 0OR X 1AND X 2

    2 X0 X1 X3

    X2

    ORG X 0AND X 1OR X 2AND X 3

    ORLD

    X3X2

    X1X0

    ORG X 2LD X 0AND X 1ORLD AND X 3

    1 2 3

    X0 M0

    X1

    X2

    X3

    M1

    M2

    M3

    LD X 0AND M 0

    LD X 1AND M 1

    ORLD

    LD X 2AND M 2ORLD LD X 3AND M 3ORLD

  • 1-10

    ANDLD

    X1

    X2

    X3

    X5 X6

    X7X4

    ANDLD

    ORG X 1 OR X 2

    LD X 3 AND X 4 LD X 5 AND X 6 ORLD

    ANDLD AND X 7

    ANDLD AND AND

    ANDLD

    X0 X1

    X3

    X2 X4Serial Block

    ANDLD

    ORG X 0 AND X 1

    LD X 2 OR X 3

    ANDLD

    AND X 4

    1 2 3

    X6X5X2

    X0 X1 X3

    X7

    X4

    ORG X 0

    LD X 1 OR X 2

    ANDLD

    LD X 3 AND X 4 LD X 5 AND X 6 ORLD OR X 7

    ANDLD

    OUT

    Y0

    ORG SHORT OUT Y 0

  • 1-11

    1.5 (WinProladder )

    ANDLD ORLD

    8

    6

    4

    5

    13

    9

    7

    3

    1

    2

    1410

    12

    11

    9

    7 8

    1

    3 6

    2 4 5 10 11

    ANDLD( )

    AND( )

    ANDLD( )

    ORLD( )

    X0 X1

    X2 X3

    ORLD( )

    X4 X5

    X6 X7

    X8 X9

    X11

    X10 Y0OR( )

    12

    ORG AND

    X0 X1

    LD AND

    X2 X3

    ORLD

    LD AND

    X4 X5

    LD

    AND

    X6 X7

    ORLD

    Y0

    ANDLD

    AND

    X8

    AND

    LD AND

    X9 X10

    OR

    X11

    OR

    ANDLD

    OUT Y0 Y0

    Y0

  • 1-12

    1.6 (TR) (WinProladder )

    1.5 1.5 TR

    * TR

    1 TR LD TRn AND OUT TRn LD TRn AND LD

    2 40 TR TR 0 1 2 TR OUT TR0 LD TR0

    3 TR ORG LD

    4 TR

  • 1-13

    1

    X0 X1

    X2

    Y0OUT TR0

    Y1

    Y2LD TR0

    AND X 0 OUT TR 0 AND X 1 OUT Y 0 LD TR 0 AND X 2 OUT Y 1 LD TR 0 OUT Y 2

    2

    X1

    X3

    Y0

    OUT TR1

    LD TR0

    X2

    X4

    X5

    X7

    X6

    X8

    X9OUT TR0

    block 1 block 2

    LD TR1

    block 3

    ORG X 1 AND X 2 LD X 3 OUT TR 0 AND X 4 ORLD OUT TR 1 AND X 5 TR ANDAND X 6 LD TR 1 TR LD TRAND X 7 LD TR 0 AND X 9 TR ANDORLD AND X 8 ORLD OUT Y 0

    2 1 2 X9 3 1 2

    * TR

    TR ANDLD

    1.7

    ORLD

    X0

    X1 X2

    X1 X2

    X0

    LD X 0

    LD X 1 LD X 1 AND X 2 AND X 2 OR X 0 ORLD

    * 1 2

    3

  • 1-14

    ANDLD

    X0 X2X1

    X3 X4

    X2

    X0 X1X3 X4

    ORG X 0

    ORG X 3AND X 1 AND X 4LD X 2 OR X 2LD X 3 AND X 0AND X 4 AND X 1ORLD ANDLD