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A FAST MULTIPLIER DESIGN USING SIGNED-DIGIT NUMBERS AND 3-VALUED LOGICI-Shi E. Chen and T. N. RajashekharaDepartment of Electrical EngineeringState University of Nev York at BinghamtonBinghamton, NY 13902-6000

Abs rd c tA multiplier design using 3-valued (ternary) logic andredundant binary signed-digit (RBSD) numbers ispresented in this paper. The use of 3-valued logicoffers the advantage of reduced circuit complexityboth i n terms of transistor count and interconnectionssince each ternary bit can support one digit of theRBSD number system. The choice of RBSD number systemenhances the speed of multiplication by allowing carryfree addition of partial products. While the internalmultiplication uses RBSD numbers, both the inputoperands and the output product are assumed to be inthe standard tvo's complement form. MAGIC and SPICEsoftvare tools vere used t o produce VLSI designlayouts and circuit simulation results.1. IntroductionIn many computer applications such as signal and imageprocessing, computer graphics, and process control,multiplication is one of the most vital functions. Thedemand placed by these applications on the speed ofmultiplication is motivating researchers to look foralternative approaches for designing high speedmultipliers. Using non-conventional number system suchas signed-digit numbers for designing fast arithmeticunits is particularly gaining much attention in recentyears. Signed-digit number system offers thepossibility of carry free addition by taking advantageof the redundancv associated vith this

in the digit set {-l,O,l} of RBSD requires only oneternary bit. Rajashekhara and Chen 1 6 1 have presenteda scheme f o r RBSD addition using ternary logic. Inthis paper, ve present the design of a multiplier unitusing the RBSD adder cells presented in 161 . Insection 2 , we shall discuss briefly signed-digitnumbers and RBSD addition. In section 3, ve shalldiscuss the multiplier design using 3-valued RBSDadders. In section 4, ve shall summarize thecontributions of this paper.2. RBSD Addition and Ternary L o g i cEach digit of a signed-digit (SDI numberrepresentation in radix r is made up of an elementfrom the digit set {-a,-(a-l),..., -1, 0, , (a-l),a) vhere a is chosen to be Lr/2r to yield mininursredundancy. An SD number vith radix 2 and digit set(-l,O,l) is called redundant binary signed-digit(RBSD) number. Addition of tvo RBSD numbers can becarried out in parallel in three steps as shown inFigure 1 and described by equations (11, ( 2 1 , and (3).An RBSD adder design using 3-valued logic is describedin [ 6 1 . Ternary logic is very suitable for designingarithmetic units using RBSD number system since eachternary bit can support one digit of the RBSD number.The truth table of ternary inverter gates used indesigning RBSD adder circuit is given in Table 1.

-=i+2epresentation. Several papers have appeared xi+l-in recent years exploring the use of

arithmetic units [l-61. Takagi et a1 [11 have rredundant binary signed-digit numbers. In thispaper, the partial products are addedpair-vise vhich reduces the number of -the vord length. Booth recoding technique is yi-also utilized to reduce the number of partialproducts are added in constant time, since thepartial products are represented in RBSD xi-*

signed-digit numbers for designing fast Yi+l- "i+li+2'resented a high speed multiplier design using I1

7 _II%+ladditions in proportion to the logarithm of wi 111 .

products by a factor of tvo. Tvo partial

number system. Rajashekhara and Kal I 4 1 have Ipresented an implementation of the same idea yi-+ W

I1 d-i'

- -1vith reduced logic complexity making itsuitable for VLSI implementation. In both thesedesigns RBSD numbers are represented using binarylogic vhich requires two bits per digit of RBSDnumber. Though these designs are able to achieveof inter connections can be significantly reduced if a

Figure 1: RESD Adder Structurehigher speeds, the circuit complexity and the numberproper choice of logic implementation compatible viththe number system is made. Ternary or 3-valued logic

xi + Yi = vi t 2*titlvi + ti = VIi t 2*t'i+lVI. t t'i = sblends itself vith RBSD number system since each digit i

CH2819- 1/90/0000-088 $01 OOO1991IEEE

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Table 1Truth t a b l e of Ternary Inve rter Gates

Input (x) output ( i )STI PTI NTI0 0 1 -11 -1 -1 -1-1 1 1 1

STI: Simple Ternary InverterPTI: Positive Ternary InverterNTI: Negative Ternary Inverter

A ternary T gate vhose function is described byequation (4) is realized using PTI and NTI gates. Anappropriate combination of T gates is used to realizethe RBSD adder functions described by equations (11,(21, and ( 3 ) .T(y1,y2,y3: x ) = yi; i = 1 if x = -1 (4)

= 2 i f x = O= 3 i f x = 1

vhere yl, y2, y3 are gate inputs, x is control input,and yi is gate output.3. RBSD Mu l t i p l i e r D e s i gnThe RBSD adder discussed above and described in I61 isutilized for adding the partial products in designingthe multiplier. Bit pair recoding 17 1 of themultiplier operand is employed to reduce the number ofpartial products by a factor of 2. Partial productsare added in a pair-vise binary tree fashion 111 vhichreduces the number of partial product pairs to beadded in proportion to the logarithm of the wordlength of the multiplier operand. Since the add timeis constant independent o f the word length, themultiplication time is of the order O(log2n) for ann-bit multiplier operand. Though the internal additionis performed on RBSD numbers, the input operands are

J A 2JA3

assumed to be in standard tvo's complement (TC) formand the RBSD product is converted back to TC form thusmaking the design suitable to be used as a buildingblock in digital systems using binary number system.Figure 2 shovs the block diagram of a 4x4 multiplierunit. The multiplier and multiplicand operands are inTC form. The partial product generator (PPG) generatesthe partial product bits in RBSD form using bit-pairrecoding technique. Figure3 shovs the circuit diagramof the PPG. This circuit is an implementation ofTable 2 which shovs the RBSD product bit as a functionof TC multiplicand and multiplier bits. The multiplierand multiplicand bits use binary logic with logic 0and 1 represented by voltage levels OV and 5Vrespectively vhile the partial product bits useternary logic vith logic -1, 0, and 1 represented byvoltage levels OV, 2.5V, and 5V respectively. Thepartial product bits should yield 0, 1, -1, 2 , or -2times the multiplicand depending on the pattern ofmultiplier bits B j t l , Bj, and Bj-l. The partialproduct bits a (-a) in columns PP. . and PPjtitlrepresent 1 (-1) and 2 (-2) times the multiplicandrespectively. Since the multiplier and multiplicandare in TC form, a 1 in the most significant bitposition of the multiplier represents a negativenumber and this is reflected in the partial product bychanging the sign of nonzero elements as seen in theright tvo columns of Table 2. An example of obtaining

3+1

the partial products is shovn belov:B5B4B3B2B1B0Multiplier 0 1 1 0 1 1 Multiplicand

Partial product corresponding to BIBOB-l1 -1 0 0 -1 0 vhich is -1 times the multPartial product corresponding to B3B2B1

ASA A 3A2A A01 1 0 0 1 0(110) ispl icand101) is

1 -1 0 0 -1 0 vhich is also -1 times the multiplicand.Partial product corresponding to B5B4B3 (011) is-1 1 0 0 1 0 0 vhich is 2 times the multiplicand.

J AOJ

PPGRBSDpp1 Product

toTC +BSD ADDER *

4TCProduct

.? ?? .?A 3 A 2 A1 AO

PPG = Partial Product GeneratorB B B B = Multiplier Operand, A A A A = Multiplicand Operand3 2 1 0 3 2 1 0

Figure 2 Block Diagram of a 4x4 Multiplier882

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To ensure proper positional veightag es each subsequentpartial product is left shifted tvo digit positionsvith respect to the previous partial product beforethe partial products are added.It may be noted here that the complete circuit ofFigure 3is used only fo r the PPG corresponding to theHSB of the multiplicand (A3 ) in Figure 2. Th e PPGcorresponding t o the next lover significant bit of themultiplicand (A Z) consists of only part a of Figure 3vith OV and 5V lines interchanged. All other PPGsconsist of only part b of Figure 3. The choice of onlyportions of Figure 3 for partial product generationsignificantly reduces the chip area for operands vithlarge vord length.

The partial products are properly aligned and addedpair-vise using RBSD adder as shovn in Figure 2. Fo rn-bit operands, rn/21 partial product s are generatedand pair-vise addition of these partial productsrequires log2rn/21 levels of RBSD adders. Sinceaddition at each level is done in constant timeindependent of operand length, the multiplicatio n timeis of order O(10g2rn/21). Hovever, t he product isavailable in RBSD form. To make the design compatiblewith other digital systems, it is desirabl e to convertthe RBSD product into TC form. The RBSD t o TCconverter block shown in Figure 2 is designed using aborrow look back ( B L B ) technique suggested byRajashek hara and Nale [51.

F i g u r e 3 C i r c u i t S c h e m a t i c of P a r t i a l P r o d u c t G e n e r a t o r ( PPG)T a b l e 2

B i t - P a i r Recoding t o Generate RBSD P a r t i a l P r od u ct B i t sMultiplier Multiplicand

Bjtl Bj Bj-l A i0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

partialppjti ppjtitl( i f A i is not MSB)0aa

-a-a-a-a0---

productppjti(if Ai0-a-a--aaa

Note: Bjtl, Bj, Bj-l, Ai are in TC form. The logic levels0 and 1 corresponds to 08 and SV respectively.x mean s don't care.a E {O,l).PPjti and PPjtitl are in RBSD form. The logic levels -1,0, and 1 corresponds to OV, 2.5V, an d 5V respectively.0 and -0 are the same a s 0.

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4. Conclusion 4. ReferencesIn this paper, we have presented a multiplier designvhich makes use of RBSD adders designed uslng 3-valuedlogic. Bit pair recoding 1s employed to generatepartial products in RBSD for0 using TC multiplier andmultiplicand operands. VLSI layouts are produced forRBSD adder and partial product generator circuitsusing MAGIC software on SUN vork station. Figures 4lnd 5 show the layouts of portions of RBSD adder andpartial product generator circuits respectively. Eachfunctional unit and the complete multiplier circuitare simulated using SPICE circuit simulation softwareto verify the correctness of design. Currently ve arevorking on the VLSI layout far a prototype of thecomplete multiplier unit including RBSD to TCconverter. Extending bit pair recoding to multi-bitrecoding [ 8 1 is an interesting approach to explore andinvestigate the trade off betveen increased circuitcomplexity of multi-bit recoding and reduced set ofpartial products.

F i g u r e 4 V L S I Layout of RBSD Adder C e l lR e p r e s e n t i n g e q u a t i o n ( l ) , F i g . 1

[11 Takagi, N. et al., "High Speed VLSI MultiplicationAlgorithm with A Redundant Binary Addition Tree,"IEEE Trans. Comput., Vol. C-34, No. 9, pp.789-796, Sept. 1985.[21 S. Kawahito, M. Kamayerna, T. Higuchi, and H. Yama-da, "A 32x32-bit Multiplier Using Multiple-valuedMOS Current-Mode Circuits," IEEE J. Solid StateCircuits, Vol. 23, No . 1, pp. 124-132, Febr. 1988.131 S. Kavahito, M. Kamayema, and T. Higuchi, Multiple-Valued Radix-2 Signed-Digit Arithmetic Circuitsfor High Performance VLSI Systems," IEEE J. SolidState Circuits, Vol. 25, No. 1, pp. 125- 131,Febr. 1990.I41 Rajashekhara, T. N. and Kal, O., "Fast MultiplierDesign Usincj Redundant Signed-Digit Numbers," toInternational Journal of Electronics, Vol. 69,1990.I51 Rajashekhara, T. N. and Nale, A. S . , "ConversionRepresenta-Electronics, Vol.from Signed-Digit to Radix Complementtion," International Journal of69, 1990.61 Rajashekhara, T. N. and I-Shi E. Chen, "A FastAdder Design Using Signed-Digit Numbers and

Ternary Logic," Proc. 1990 IEEE Southern TierTechnical Conference, pp. 187-194, Binghamton, NewYork, April 1990.

McGraw-Hill 1984.7 1 J. J. F . Cavanagh, "Digital Computer Arithmetic,"

( 8 1 H. Sam and A. Gupta, "A Generalized Multi-bitRecoding of TWO'S Complement Binary Numbers andIts Proof vith Applications in Multiplier Impleme-ntations," IEEE Tr. Computers, Vol. 39, No. 8, pp.1006-1015, Aug. 1990.

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F i g u r e 5 V L S I Layout of P a r t i a l P r o du c t G e n e r a t o r F i g u r e 3.

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