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A Novel Flash Fast-Locking Digital PLL:

VHDL-AMS and Matlab/Simulink Modeling and SimulationsBy

Dr. Mahmoud Fawzy Wagdy

Professor of Electrical Engineering,

California State University, Long Beach (CSULB),

1250 Bellflower Blvd., Long Beach, CA 90840, USA&

Anurag Nannaka, MSEE, CSULB,

M4 Wind Services,

5800 Skylab Rd., Huntington Beach, CA 92647, USA&

Rajeev K. N. Channegowda, MSEE, CSULB,

1250 Bellflower Blvd., Long Beach, CA 90840, USA

ABSTRACT - A novel flash fast-locking digital phase-locked loop (DPLL) is presented and

 behaviorally modeled. The DPLL operation includes

two stages: (1) a novel coarse-tuning stage for

frequency tracking which employs a flash algorithmsimilar to the one employed in flash A/D converters

(ADCs) and (2) a fine-tuning stage similar to

conventional (classical) DPLLs. The coarse-tuningstage includes an array of frequency comparators, a

 priority encoder, a digital-to-analog converter

(DAC), and control logic. Design considerations and

implementations are presented in this paper. VHDL-

AMS (Simplorer) and Matlab/Simulink are used to

design and perform simulations. The fast-lockingDPLL reduces the lock time by a factor of about 1.80

compared to its conventional DPLL counterpart.

Key Words:  PLL, DPLL, fast-locking, coarse

tuning, frequency tracking, flash algorithm, fine

tuning, phase tracking, lock time, behavioral

modeling, VHDL-AMS, MATLAB, SIMULINK.

I. INTRODUCTION

Phase-locked loops (PLLs) are most common in

applications like wireless transceivers, cellular phones, etc. One of the important characteristic of

a PLL is its lock time, which is amount of time a

PLL takes to adapt and settle down to the changes in

the input frequency. Conventional DPLL’s employ

the technique of phase tracking which makes themmisfits for contemporary high-speed high-throughput

technology. The literature on conventional

(classical) PLLs contains several thousands of

designs and research papers, e.g. [1].

Fast locking is therefore a necessity for clock/

data recovery circuits, frequency-hopping spread-

spectrum communications, information technology,

etc. However the literature on fast-locking PLLs isrelatively very limited due to their more recent

demand. Example research papers include: [2-5].

Examples US patents include: [6-8]. A number ofindustrial corporations produce fast-locking PLLs, e.g.

Analog Devices Inc. [9], True Circuits Inc. [10], and

 National Semiconductor Inc. [11].

Frequency tracking is an effective frequency

comparison technique which has a huge potential todecrease the lock time. Although some techniques

have been employed to achieve effective frequency

comparison, most of these techniques rely on countingthe outputs of the phase frequency detector (PFD) todetermine which frequency is higher. This process still

depends on the phase of the signal resulting in high

comparison time. In this paper, a standard frequency

comparison technique is used which does not dependon the phase of the input signals.

II. THEORY OF OPERATION

The block diagram of the novel flash DPLL

employing DAC is shown in Fig. 1, which is similar

to [12, Fig. 1] except that the DAC output is appliedhere to the LPF rather than directly to the VCO. It

comprises two modes of operation, namely coarse

tuning followed by fine tuning. Coarse tuning involves

Frequency Comparator Array (FCA), Priority Encoder

(PE), and a DAC. Fine tuning consists of Phase

Frequency Detector (PFD), Charge Pump (CP),Lowpass Filter (LPF) and Voltage-Controlled

Oscillator (VCO).

2011 Eighth International Conference on Information Technology: New Generations

978-0-7695-4367-3/11 $26.00 © 2011 IEEE

DOI 10.1109/ITNG.2011.136

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this design) thus starting a new frequency

comparison cycle.The frequency comparator used in this work has

three outputs (High, Low, and Timeout). Output High

=’1’ when F_input > F_vco, thus the voltage to the

VCO must be increased so that F_vco catches up with

F_input. Similarly, output Low=’1’ when F_input <

F_vco, thus the voltage to the VCO must bedecreased so that F_vco catches up with F_input. The

FC schematic is given in Fig. 2.

Fig. 2. Frequency Comparator Using Ring Counters

In cases when F_input and F_vco are close to

each other the FC cannot decide during the allotted

time (20ns in this case). To account for these cases, a

Time-Out signal is added to the output of the FC. The

idea is that ‘Time-Out = 1’ means that both F_inputand F_vco are too close to each other, accordingly

coarse tuning can be stopped and fine tuning can be

started.

E. Frequency Comparator Array (FCA)

Frequency Comparators are arranged in the form

of an array, as shown in Fig. 3, to accomplish fast

locking employing the Flash algorithm. Each FC is provided with a reference frequency input.

In this design, the FCA is composed of seven

FCs, with 7 different reference frequencies which areequi-spaced over a frequency range of 2GHz. When

F_in changes, the FCA start a comparison cycle at the

end of which the FCA output is called “Thermometer

Code”. The thermometer codes “0000000” through

“1111111” correspond to the following F_in eightfrequency ranges respectively: F_in

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  Table 2. DAC Output Versus Encoder Output

D2 D1 D0 VOLTAGE (Vctnl)

0 0 0 -3.3 V

0 0 1 -2.5 V

0 1 0 -1.67 V

0 1 1 -0.83V1 0 0 0 V

1 0 1 0.83 V

1 1 0 1.67 V

1 1 1 2.5V

At this moment, if the switch is hypothetically

 brought back to its initial position to start fine tuning,

the capacitors cannot hold on to the voltage as it

slowly discharges, which causes a bigger kink in the

LPF output voltage versus time. To prevent thiscondition, a monostable multivibrator is used, which

 produces an output pulse with a fixed duration called“oneshotoutputpulse”, to control the switch, the

 period of which is chosen to be 40ns. For smooth

transition between coarse tuning and fine tuning, the

capacitor voltages should be almost fully charged to

the DAC output within 40ns.

IV. DESIGN USING VHDL-AMS

Modeling and design of some example Flash

DPLL blocks in Section III are given below.

A. Phase Frequency Detector (PFD)Fig. 4 describes part of the implementation.

Fig. 4. Part of Phase Frequency Detector

B. Lowpass Filter (LPF)The LPF is described in Fig. 5. The

component values given are, for example, C1=1pF,

C2=10pF, and R2= 300 .

Fig. 5. Lowpass Filter

C. Voltage-Controlled Oscillator (VCO)

The VCO is modeled as shown in Fig. 6. In the

example given, the VCO operating frequency isassumed to be from 80MHz to 2GHz.

Fig. 6. Voltage-Controlled Oscillator

D. Frequency Comparator (FC)The FC is modeled as shown in Fig. 7.

Fig. 7.  Frequency Comparator

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V. VHDL-AMS SIMULATIONS

A. Lock-Time ComputationThe conventional DPLL is composed only of a

PFD, CP, LPF, and a VCO, while the Flash DPLL is

shown in the Fig. 1. The lock time for the DPLL is

calculated by performing several positive andnegative frequency hops. The DPLL is said to be

locked when the control voltage to the VCO becomes

constant and ripple-free while the phase difference

 between F_input and F_vco is zero or constant.

B. Locking Plots for Classical and Flash DPLLs

Fig. 8 is a plot of VCO control voltage versus

time for both the flash DPLL and its classical DPLLcounterpart. The results correspond to the case “ =

0.4”. Fig. 8(b) clearly demonstrates flat response

during the one-shot 40ns pulse.

(a)  Lock Time = 820-500 = 320ns

(b)  Lock Time = 480-300 = 180ns

Fig. 8. VCO Control Voltage Versus Time for theFrequency Hop 1.7GHz-250MHz

(a) Classical DPLL, (b) Flash Fast-Locking DPLL

C. Simulations & Comparison Table

Table 3 compares the lock times of the Flash

Fast- Locking DPLL and its classical DPLL counter-

 part for various positive and negative frequency hops.

The table reveals a lock-time improvement by a ratio

of 1.802 on the average.

The Flash DPLL was also designed using the

following parameters: Fmax = 1.81GHz, Fmin = 200

MHz, Vmax=2.66V, Vmin=-2.66V, Ipump= 400µA,

R2= 300 , C2= 10pF, and C1= 1pF, i.e. = 0.066.

Simulations revealed a lock-time improvement by a

ratio of 2.30 on the average.

Table 3. Comparison Between Flash Fast-LockingDPLL and Classical DPLL Lock Times

FrequencyHop

ClassicalDPLL

(ns)

FlashDPLL

(ns)400–900MHz 220 130

900M-1.6GHz 280 160

600M-1.45GHz 360 180

400M-1.4GHz 360 170

250M-1.7GHz 390 190

900M-450MHz 190 130

1.6G-900MHz 240 160

1.45G-600MHz 280 140

1.4G-400MHz 280 1801.7G-250MHz 320 180

VI. DESIGN USING

MATLAB/SIMULINK

Modeling and design of some example Flash

DPLL blocks are given below.

A. Phase Frequency Detector Unlike other Phase Detectors (PDs), the PFD

output signal not only relies on phase error but alsoon frequency error. Since the PFD knows at all times

whether F_in is greater or less than F_vco, it provides

 better locking for large frequency offset between the

two signals. The PFD has three states, as shown in

Fig. 9.

Fig. 9. State Flow Implementation of PFD

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  On every rising edge of data (Fin), the statechanges from 0 to 1, and an up signal is generated. If

in state 0 and a rising edge of dclock (Fvco) occurs, the

state changes from 0 to 2, a dn signal is generated.

However, if in state 1 and a rising edge of dataoccurs, it remains in state 1 and the up signal also

remains 1. Similarly in state 2, a rising edge of dclock

remains in the same state and dn remains 1.

The RPG employs a Matlab Pseudo-Random

Integer Generator as shown in Fig. 11. The RPGL

 produces reference frequencies at various phases. It

helps testing the robustness of the FCA in use.

B. FCA & Random Phase Generator LogicThe Frequency Comparator Array (FCA)

constantly monitors the input frequency every 20ns.

After the first 20ns it will output a thermometer code.If the input frequency has not changed within the

20ns, the outputs will be unchanged. Two cycles of

20ns each are needed; the first detects the mere

change in F_in but the second gives a reliable

comparison result; thus a total of 40ns is needed

Fig. 10. Frequency Comparator Array Schematic

Fig. 11. Random Phase Generator Logic (RPGL)

 before coarse tuning starts. Due to the random phase

of the seven reference frequencies (Frefs) connected

to the FCs, a Random Pulse Phase Generator is

connected to all 7 Frefs of the FCs as shown in Fig.10.

C. Charge Pump, Lowpass Filter, and Monostable

Multivibrator Block

A switch is placed at the input of the LPF. The

DPLL is in fine tuning/coarse tuning stage when thecontrol signal of switch is LOW/HIGH respectively.

The control signal is generated by the control logic

and monostable multivibrator block, as shown in Fig.12. The control logic circuit outputs HIGH when it

notices a change in the encoder output. This triggers

the monostable ensuring it to maintain HIGH position

for 40ns duration. During this time, the DAC output

value is constantly applied to the lowpass filter.

Fig. 12. Charge Pump, Lowpass Filter, andMonostable Multivibrator Block

VII. MATLAB/SIMULINK

SIMULATIONS

A. Lock-Time Computation

In order to compare the lock times of the VHDL-

AMS design with those of the Matlab/Simulink design,the same values for all circuit components and

 parameters are used. These are given in the Appendix,

namely, Kvco, Ipump, C1, C2, and R2. Simulationswere thus performed for the same damping factor .

The lock time for the DPLL is calculated by

Performing several positive and negative frequencyhops, which are identical to those hops used in the

VHDL-AMS design. The DPLL is said to be locked

when the control voltage to the VCO becomesconstant and ripple-free while the phase difference

 between F_input and F_vco is zero or constant.

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B. Locking Plots for Classical and Flash DPLLFig. 13 is a plot of the VCO control voltage

Vcntrl versus time as well as the phase shift between

F_in and F_vco , for both the flash DPLL and its

classical DPLL counterpart. The results correspond tothe case “=0.4”. Fig. 13(b) clearly shows flat

response of Vcntrl during the one-shot 40ns pulse.

(a)  Lock Time = 990-600 = 390ns

(b)  Lock Time = 765-600 = 165ns

Fig. 13. VCO Control Voltage (Vcntrl) Versus Time

for the Frequency Hop 1.7GHz-250MHz(a) Classical DPLL, (b) Flash Fast-Locking DPLL

It is also interesting to notice that the right-most

vertical colored lines in both Figs. 13(a) and 13(b)

correspond to the last moment when there is a phaseshift between F_in and F_vco, i.e. phase locking. It is

also noted that there is a reasonable agreement

 between Fig. 8 and Fig. 13, thus the VHDL-AMS andMatlab/Simulink results verify one another.

C. Simulations & Comparison Table

Table 4 compares the lock times of the Flash

Fast-Locking DPLL and its classical DPLL counter-

 part for various positive and negative frequency

hops. The table reveals a lock-time improvement by a

ratio of 1.73 on the average. This is again in

reasonable agreement with the outcome of Table 3 of

the VHDL-AMS results.

Table 4. Comparison Between Flash Fast- Locking

DPLL and Classical DPLL Lock Times

FrequencyHop

ClassicalDPLL

(ns)

Flash DPLL(ns)

400-900MHz 210 185

900M-1.6GHz 240 190

600M-1.45GHz 265 150

400M-1.4GHz 305 190

250M-1.7GHz 395 165

900M-450MHz 205 160

1.6G-900MHz 240 150

1.45G-600MHz 270 140

1.4G-400MHz 290 130

1.7G-250MHz 390 165

VIII. CONCLUSIONSClassical DPLL’s employ phase tracking which

takes long time to lock, thus they become misfits for

contemporary high-speed applications. Fast locking is

therefore a necessity for clock/data recovery circuits,

frequency-hopping spread-spectrum communications,

cellular phones, etc.

A novel Fast-Locking DPLL is presented and behaviorally modeled using VHDL-AMS (Simplorer)

and Matlab/Simulink. It employs two stages: (1) a

novel coarse-tuning stage, employing a flashalgorithm similar to the one employed in flash ADCs,

for frequency tracking to reduce the lock time and (2)

a fine-tuning stage for phase tracking which is similarto conventional (classical) DPLLs. The flash section

consists of a frequency comparator array, a priority

encoder, a DAC, and control logic including amonostable multivibrator. Coarse tuning takes a total

of 80ns, which includes (1) 40ns to create a valid

thermometer code for the new input frequency, afterthe hop, and to perform frequency translation for the

VCO output frequency, and (2) 40ns for the one shot

 pulse duration. Coarse tuning then switches control to

fine tuning until the DPLL is completely locked.

Simulation results have consistently shownconsiderable lock time improvement for all the

damping factors considered, namely = 0.066, 0.1,0.4, 0.7, and 1.0. The results detailed in this paper arefor the case =0.4. VHDL-AMS and Matlab/Simulink

simulations are in close agreement and confirm one

another. These results demonstrated a lock-time

improvement by a factor of 1.8 and 1.73 respectively,

on the average, in the frequency range 200MHz-2GHz.

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IX. APPENDIX

DPLL DESIGN EQUATIONS

Using [13]:

VCO formula          300 MHz/vFo (Free Running Frequency) = 1GHz

Let Ipump = 500µA,

C2 = 20pF & C1= 0.2C1= 4pF.

    

  = Natural Frequency

  µ     Mrad/secTo get different resistor values for different damping

fac    0.1, 0.4, 0.7 and 1, we use:tors , namely

   , thus:

 

 

Hence we get R2 = 290 , 1.158 K , 2.026 K,

2.895K for = 0.1, 0.4, 0.7, 1.0 respectively.

X. ACKNOWLEDGEMENT

This work was sponsored by the US-Egypt

Science and Technology Joint Fund in cooperation

with the National Science Foundation under NSF

Grant No. 0710887.

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