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    III. BALANCED TRANSIMPEDANCE AMPLIFIER

    The transimpedance amplifier, along with a model ofthe photodiode, is shown in Fig. 2. The circuit has abalanced structure consisting of an input differential pairfollowed by a pair of common-source second stages thatutilize shunt feedback. Although, the basic structure followsthe design reported by Coppoolse et al.[3], significant

    changes were made to adapt their original 5-V design for3-V operation. Specifically, we reduced the number ofstages from three to two, replaced all biasing resistors withactive current sources, and introduced a p-type input stageto create a complementary structure.

    The transimpedance amplifier uses a p-type input stage

    for a number of reasons. Because the depletion capacitanceof a photodiode is inversely proportional to its reverse biasvoltage, Vbias, high speed is achieved by maximizingVbias. For example, increasing Vbias from 1-V to 2-V onthe Temic BPV-10NF PIN photodiode changes thedepletion capacitance from 6.6 pF to 5.2 pF -- a significant20% reduction. With a p-type differential pair, the inputscan be set near ground to maximize Vbias without fear ofsaturation. In addition, setting the input levels low ensures alarge voltage drop across the tail current source, allowingthe use of cascode devices to improve current matchingbetween the tail current and the active loads. Goodmatching is important in this design because the lack ofcommon-mode feedback implies any mismatch in the

    currents will be fed into the second stage, producing anoffset at the output. Finally, p-type inputs necessitate an-type second stage which is beneficial since the highermobility of n-type devices help to place the non-dominantpoles of the circuit higher in frequency, allowing fasteroperation and improved stability.

    Two interesting properties resulting from the localfeedback are the circuits inherent low output impedanceand the natural biasing of the output common-mode level.The low output impedance can be deduced by realizing thatdevices M5 and M6 are now diode-connected through their

    Fig. 2 Balanced transimpedance amplifier with shunt feedback.

    M1 M2

    M7

    M8

    M5 M6

    M3

    M4

    bias4

    bias3

    bias1

    bias2

    Vin- Vin+

    Vout+Vout-

    1 2

    Rf1Rf1

    Rf2Rf2

    Cf1Cf1

    Cf2Cf2

    M10

    M9

    CdCd

    is

    io io

    respective resistors. Assuming that is notextremely large, the output impedance is equal to theinverse of the transconductances of M5 and M6 which is onthe order of a few hundred ohms. A low output impedanceallows us to eliminate the output source follower stage usedin [3] to achieve an improved phase response. The outputcommon-mode voltage is naturally set to .

    Having explained the basic structure of thetransimpedance amplifier, we now present the main designequations. Although the photocurrent signal issingle-ended, the final output is differential; therefore, thecircuits differential behavior is considered whencharacterizing the signal path. The transimpedance gain ofthe circuit is given by

    (1)

    where Avdis the open-loop voltage gain of the amplifier. Bysymmetry, Avd can be determined by analyzing the left

    half-circuit of Fig. 2. Because the second stage has a lowinput impedance roughly equal to the inverse of thetransconductance, , the intermediate current from thedifferential pair, , is effectively steered into resistor .Small-signal analysis reveals that the second stage has atransimpedance of

    . (2)

    The overall gain is the product of the two gain stages:

    (3)

    which is typically in the range of 10 to a few hundred.

    The procedure for optimizing the circuit for a givenbandwidth involves analyzing the loop gain. Because thefeedback network consists of in series withphotodiode depletion capacitance, , the dc loop gain isequal to the differential voltage gain given in equation (3).Because is typically quite large (e.g. ~ 5 pF), thedominant pole is located at the input and is given by

    . (4)

    From Equations (3) and (4), it is clear that the dominant

    pole is independent of the dc loop gain. As a result, thebandwidth of the circuit is proportional to Avd, and in orderto increase the bandwidth, both and should bemaximized. While transconductance is ultimatelylimited by power constraints, resistance is limited bythe resistors effect on the non-dominant poles in the secondstage. Small-signal analysis reveals that a pair of complexpoles are introduced by the second stage. In practice, thefeedback capacitor, , is relatively small compared toboth the total capacitance on node-1, , and the totalcapacitance at the output node, . The resulting pole

    R f1 R f1

    Vgs5,6 0.9V

    vout+ vout-

    is----------------------------

    Avd

    1 Avd+------------------- R f2=

    R f2 for Avd 1

    gm5io R f1

    vout+

    io-----------

    1 gm5R f1( )rd s5

    1 gm5rd s5+-------------------------------------------- R f1=

    Avdvout+

    vin ------------=

    vout+

    io-----------

    io

    vin ---------=

    gm1R f1

    R f2Cd

    Cd

    wp11

    R f2Cd----------------=

    gm1 R f1gm1

    R f1

    Cf1C1

    Cout+

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    locations are given by

    (5)

    . (6)

    From Equation (5), we see that the upper limit of is setby the desired bandwidth of the circuit: to ensure stability,the unity loop gain frequency should not exceed . It isuseful to note that while is inversely proportional to thesquare root of , the dominant pole, , is inverselyproportional to . Thus if during implementation,could be made to track , stability is insured because thedominant pole would drop faster than the non-dominantpole if ever increased past its nominal value. We alsosee from equation (6) that capacitor plays a dominantrole in determining the Q-factor of the poles. Thus,can be used to tailor the response of the second stage tohave a maximally-flat frequency response.

    The other feedback capacitor, , also serves to tailorthe overall frequency response by introducing a zero in theleft-half plane at

    . (7)

    This zero compensates for the 90 phase lag that isgenerated by the series feedback network.

    To illustrate the design process using a 0.35-m CMOStechnology, we optimized the transimpedance amplifier fora bandwidth of 100 MHz while limiting the power

    dissipation to 10 mW. For the given power, we achieve atransconductance of 4.4-mA/V for the first stage, and3.6-mA/V for the second stage. From equation (5), we findthe largest value to be 20 k which places the complexset of poles at around 136 MHz, sufficiently beyond the100-MHz bandwidth. By setting =60 fF, we achieve aQ-factor of 0.8 which produces a nearly maximally-flatresponse for the second stage. To determine the optimumvalue of for a 100 MHz bandwidth, we first calculatethe dc loop gain which turns out to be 72. If we set thegain-bandwidth to 100 MHz, the dominant pole, ,should be located at . Substitutinga photodiode capacitance of 5pF into Equation (4), isdetermined to be 23 k and so we round it down to 20 k

    in order to equal . Finally, fine tuning the zero locationfor lead compensation, we set to 60 fF. Simulationwaveforms of the transimpedance amplifier are shown inFig. 3; the preamplifier has a bandwidth of 120 MHz and aninput-referred noise current of 1.3 pA/ . These resultsare favorable compared with those presented in [3]: with atechnology about four times faster, we achieve over twicethe gain and our bandwidth is only about 40% lower eventhough the photodiode capacitance is over ten times larger.Having completed the design of the transimpedanceamplifier, we are ready to incorporate it into the dcphotocurrent rejection circuit.

    jX

    X

    o

    2Q-------

    o

    gm5

    Cout+C1R f1------------------------------

    Q

    1

    Cf1---------

    Cout+C1

    gm5R f1--------------------

    R f1

    oo

    R f1 p1R f2 R f2

    R f1

    R f1Cf1

    Cf1

    Cf2

    z1

    R f2Cf2-------------------=

    R f2-Cd

    R f1

    Cf1

    R f2

    p1100 72 MHz 1.3MHz

    R f2

    R f1Cf1

    Hz

    IV. DC PHOTOCURRENT REJECTION

    As described earlier, our dc photocurrent rejectioncircuit uses negative feedback to minimize the averagedifferential output voltage. Fig. 4a) shows representativedifferential outputs from the preamplifier when no dcphotocurrent is present and the active cancellation is off.When a dc component is added, the outputs shift away fromeach other as in Fig. 4b), resulting in an positive,common-mode offset. When the active cancellation isenabled, the positive offset causes the error amplifier toraise the gate voltage of transistor, Mctl, causing the deviceto begin drawing the dc component away from thepreamplifier input. When the outputs have settled, both theoffset due to the dc photocurrent as well as the averagesignal level have been eliminated as in Fig. 4c).

    The elimination of the average signal current is not aconcern so long as the low-frequency cut-off point issufficiently below the signal spectrum. For our system wehave specified a cut-off frequency of 1 MHz which issufficiently low for a 100 MHz bandwidth, and adequatelyhigh to attenuate the fluctuating light levels produced byartificial light sources, and in particular, fluorescent lamps

    Fig. 3 Simulation results of the transimpedance amplifier:

    a) Differential outputs for a 1A input pulse

    current, b) Transimpedance frequency response.

    a)

    b)

    Transimpedance(dB)

    100 kHz 100 MHz 10 GHz0

    20

    40

    60

    80

    0 10 20 30 40 50

    970

    980

    990

    Voltage(mV)

    Time (nsec)

    90

    Fig. 4 Differential output waveforms: a) no dc photocurrent,

    b) dc photocurrent added, c) steady-state.

    a) b) c)

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    with electronic ballasts[9].

    The characteristics of the dc photocurrent rejectioncircuit can be derived by studying the loop gain of the outerfeedback loop. The residual dc photocurrent entering the

    preamplifier is inversely proportional to the open-loop gainat dc. As well, the low frequency cut-off point, , isgiven by the unity loop-gain frequency. The open-loop gain,L(s), is given by

    (8)

    where is the frequency response of the erroramplifier, and constant, , is determined by thegeometry of Mctl and the CMOS process parameters.Because the bandwidth of this feedback loop is low, thefrequency response of the error amplifier can be modeledusing a single-pole response of

    (9)

    where is the dominant-pole frequency and Ao is thedc gain. The gain-bandwidth product of this circuit is

    (10)

    which leads to the following relationship between the lowfrequency cut-off point and the dc photocurrent:

    (11)

    The main observation from Equations (8) and (11) isthat both the open-loop gain and cut-off frequency areaffected by the dc photocurrent level. Fig. 5 shows the

    simulated frequency response of the circuit incorporatingour optimized transimpedance amplifier. From 5 A downto 5 nA, the curves show how decreasing the dcphotocurrent degrades the regulation while shifting downthe cut-off frequency. Yet this situation is not as onerous asit would first appear once we look at the possible situations.True, the dc regulation is poor when there is littlephotocurrent, but when there is little photocurrent, dcregulation is not required; when the dc photocurrent level ishigh, so is the effective regulation. Thus, the feedback loopperforms well in situations where it is truly needed.

    cut_off

    L s( ) gmctlR f2Aer r s( )=

    Kct l IdcR f2Aer r s( )=

    Aer r s( )Kct l

    Aer r s( ) Ao1 s er r+--------------------------=

    er r

    L jer r( ) er r1 cut_off=

    cut_off er rKct lR f2Ao Idc=

    Fig. 5 Frequency response of preamplifier with dc

    photocurrent rejection for different current levels.

    Transimpedance(dB)

    5nA

    50nA

    500nA

    5A

    0

    20

    40

    60

    80

    100Hz 100MHz 10 GHz

    90

    10kHz 1MHz

    The dependency of the cut-off frequency on the dcphotocurrent does pose a concern in the case of largephotocurrents. For instance, from Fig. 5 we see that beyond500-nA, the cut-off frequency exceeds our 1 MHzspecification, and at 5A, the loop gain has increased to thepoint that it begins affecting the passband response of thetransimpedance amplifier. Ideally, we would like some

    method of limiting the photocurrent which passes throughtransistor Mctl. A potential solution would be to redirect theexcess photocurrent into another current source that isstatic, but which can be switched on when needed. In thisway the new current source does not change the loopdynamics, but simply off-loads some of the currenttransistor Mctl would otherwise need to draw.

    V. SUMMARY

    This paper proposes an optical receiver structure foruse in infrared wireless communications. The structureactively rejects dc photocurrents using negative feedbackaround the core transimpedance amplifier. The rejectionperformance was shown to improve with increasing

    photocurrent levels.

    The differential, shunt-feedback transimpedanceamplifier exhibits good performance, and we have shownhow it can be adapted for low-voltage CMOS technology.Simulation results show the preamplifier provides a gain of20 k over a bandwidth from 1 MHz to 100 MHz with aninput noise current density of 1.3 pA/ . The opticalpreamplifier is currently being fabricated using a 0.35 mCMOS process.

    VI. REFERENCES

    [1] M. Nakamura et al., An Instantaneous Response CMOS OpticalReceiver IC with Wide Dynamic Range and Extremely High

    Sensitivity Using Feed-Forward Auto-Bias Adjustment, IEEE J.Solid-State Cir., Vol. 30, No. 9, pp. 991-997, Sept. 1995.

    [2] M. Ingels, G. Van der Plas, J. Crols, and M. Steyaert, A CMOS 18THz-ohms 240 Mb/s Transimpedance Amplifier and 155Mb/sLED-Driver for Low Cost Optical Fiber Links, IEEE J. Solid-StateCir., Vol. 29, No. 12, pp. 1552-1559, Dec. 1994.

    [3] R. Coppoolse, J. Verbeke, P. Lambrecht, J. Codenie, and J.Vandewege, Comparison of a Bipolar and a CMOS Front End inBroadband Optical Transimpedance Amplifiers, Proc. 38th MidwestSymp. on Cir. and Sys., Brazil, pp. 1026-1029, Aug. 1996.

    [4] S.B. Alexander, Optical Communication Receiver Design, SPIE Press,Bellingham, Wash., 1997.

    [5] B. Nauta, A CMOS Transconductance-C Filter Technique for VeryHigh Frequencies, IEEE J. Solid-State Cir., Vol. 27, No. 2, pp.142-153, Feb. 1992.

    [6] M.B. Ritter, F. Gfeller, W. Hirt, D. Rogers, and S. Gowda, Circuit andSystem Challenges in IR Wireless Communication, IEEE Intl

    Solid-State Cir. Conf., pp. 398-399, San Francisco, CA, Feb. 1996.[7] R.G. Swartz, Y. Ota, M.J. Tarsia, and V.D. Archer, A Burst Mode,

    Packet Receiver with Precision Reset and Automatic Dark LevelCompensation for Optical Bus Communications, Symp. on VLSITechnology, Kyoto, Japan, pp. 67-68, May 1993.

    [8] A. Tanabe et al., A Single Chip 2.4 Gb/s CMOS Optical Receiver ICwith Low Substrate Crosstalk Preamplifier, IEEE Intl Solid-StateCir. Conf., pp. 304-305, San Francisco, CA, Feb. 1998.

    [9] A.J.C. Moreira, R.T. Valadas, A.M. de Oliveira Duarte,Characterization and Modelling of Artificial Light Interference inOptical Wireless Communication Systems, IEEE 6th Intl. Symp. onPersonal Indoor Mobile Radio Communications, Toronto, Canada,vol.1, pp. 326-331, Sept. 1995.

    Hz

    0-7803-4455-3/98/$10 00 (c) 1998 IEEE