ltc3707egn

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LTC3707

1

3707fb

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

High Efficiency, 2-PhaseSynchronous Step-Down

Switching Regulator

The LTC3707 is a high performance dual step-downswitching regulator controller that drives N-channelsynchronous power MOSFET stages. A constant frequencycurrent mode architecture allows adjustment of thefrequency up to 300kHz. Power loss and noise due to theESR of the input capacitors are minimized by operatingthe two controller output stages out of phase.

OPTI-LOOP compensation allows the transient response tobe optimized over a wide range of output capacitance and

ESR values. The precision 0.8V reference and power goodoutput indicator are compatible with future microprocessorgenerations, and a wide 3.5V to 30V input supply rangeencompasses all battery chemistries.

A RUN/SS pin for each controller provides both soft-startand optional timed, short-circuit shutdown. Currentfoldback limits MOSFET dissipation during short-circuitconditions when overcurrent latchoff is disabled. Outputovervoltage protection circuitry latches on the bottomMOSFET until VOUT returns to normal. The FCB modepin can select among Burst Mode operation, constant

frequency mode and continuous inductor current modeor regulate a secondary winding.

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter

180 Phased Dual Controllers Reduce RequiredInput Capacitance and Power Supply Induced Noise

OPTI-LOOP Compensation Minimizes COUT 1.5% Output Voltage Accuracy over Temperature Dual N-Channel MOSFET Synchronous Drive Power Good Output Voltage Monitor DC Programmed Fixed Frequency 150kHz to 300kHz Wide VIN Range: 4.5V to 28V Operation Very Low Dropout Operation: 99% Duty Cycle Adjustable Soft-Start Current Ramping Foldback Output Current Limiting Latched Short-Circuit Shutdown with Defeat Option Output Overvoltage Protection Remote Output Voltage Sense Low Shutdown IQ: 20A 5V and 3.3V Standby Regulators Selectable Constant Frequency, Burst Mode

Operation or PWM Operation Small 28-Lead Narrow SSOP Package

Notebook and Palmtop Computers, PDAs Battery Chargers Portable Instruments Battery-Operated Digital Devices DC Power Distribution Systems

L, LT, LTC, LTM, Burst Mode, and OPTI-LOOP are registered trademarks of Linear TechnologyCorporation. All other trademarks are the property of their respective owners. Protected by U.S.Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6304066, 6580258.

+4.7F D3 D4

D1 M2

M1

CB1, 0.1F

R2105k1%

1000pF

L16.3H

CC1220pF

1FCERAMIC

CIN22F50VCERAMIC

+ COUT147F6VSP

RSENSE10.01

R120k1%

RC115k

VOUT15V5A

D2M4

M3

CB2, 0.1F

R463.4k1%

L26.3H

CC2220pF

1000pF

+COUT56F

6VSP

RSENSE20.01

R320k1%

RC215k

VOUT23.3V5A

TG1 TG2

BOOST1 BOOST2

SW1 SW2

BG1 BG2

SGND PGND

SENSE1+ SENSE2+

SENSE1 SENSE2

VOSENSE1 VOSENSE2

ITH1 ITH2

VIN INTVCC

RUN /SS1 RUN /SS2

VIN5.2V TO 28V

M1, M2, M3, M4: FDS6680A3707 F01

CSS10.1F

CSS20.1F

LTC3707

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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Input Supply Voltage (VIN) .........................30V to 0.3VTop Side Driver Voltages

(BOOST1, BOOST2) ................................... 36V to 0.3VSwitch Voltage (SW1, SW2) ......................... 30V to 5VINTVCC, EXTVCC, RUN/SS1, RUN/SS2, (BOOST1-SW1),(BOOST2-SW2), PGOOD .............................. 7V to 0.3VSENSE1+, SENSE2+, SENSE1,SENSE2 Voltages .........................(1.1)INTVCC to 0.3VFREQSET, STBYMD, FCB Voltage ......... INTVCC to 0.3VITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ... 2.7V to 0.3VPeak Output Current

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ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

gmGBW1, 2 Transconductance Amplifier GBW ITH1, 2 = 1.2V; (Note 4) 3 MHz

IQ Input DC Supply CurrentNormal ModeStandbyShutdown

(Note 5)EXTVCC Tied to VOUT1 = 5VVRUN/SS1, 2 = 0V, VSTBYMD > 2VVRUN.SS1, 2 = 0V, VSTBYMD = Open

35012520 35

AAA

VFCB Forced Continuous Threshold l 0.76 0.800 0.84 V

IFCB Forced Continuous Pin Current VFCB = 0.85V 0.30 0.18 0.1 A

VBINHIBIT Burst Inhibit (Constant Frequency)Threshold

Measured at FCB pin 4.3 4.8 V

UVLO Undervoltage Lockout VIN Ramping Down l 3.5 4 V

VOVL Feedback Overvoltage Lockout Measured at VOSENSE1, 2 l 0.84 0.86 0.88 V

ISENSE Sense Pins Total Source Current (Each Channel); VSENSE1, 2 = VSENSE1+, 2+ = 0V 90 60 A

VSTBYMD MS Master Shutdown Threshold VSTBYMD Ramping Down 0.4 0.6 V

VSTBYMD KA Keep-Alive Power On-Threshold VSTBYMD Ramping Up, RUNSS1, 2 = 0V 1.5 2 V

DFMAX Maximum Duty Factor In Dropout 98 99.4 %

IRUN/SS1, 2 Soft-Start Charge Current VRUN/SS1, 2 = 1.9V 0.5 1.2 A

VRUN/SS1, 2 ON RUN/SS Pin ON Threshold VRUN/SS1, VRUN/SS2, Rising 1.0 1.5 2.0 V

VRUN/SS1, 2 LT RUN/SS Pin Latchoff ArmingThreshold

VRUN/SS1, VRUN/SS2, Rising from 3V 4.1 4.75 V

ISCL1, 2 RUN/SS Discharge Current Soft Short Condition VOSENSE1, 2 = 0.5V;VRUN/SS1, 2 = 4.5V

0.5 2 4 A

ISDLHO Shutdown Latch Disable Current VOSENSE1, 2 = 0.5V 1.6 5 A

VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V, VOSENSE1, 2 = 5Vl

6562

7575

8588

mVmV

TG1, 2 trTG1, 2 tf

TG Transition Time:Rise TimeFall Time

(Note 6)CLOAD = 3300pFCLOAD = 3300pF

6060

110110

nsns

BG1, 2 trBG1, 2 tf

BG Transition Time:Rise TimeFall Time

(Note 6)CLOAD = 3300pFCLOAD = 3300pF

5050

110100

nsns

TG/BG t1D Top Gate Off to Bottom Gate On DelaySynchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 80 ns

BG/TG t2D Bottom Gate Off to Top Gate On DelayTop Switch-On Delay Time CLOAD = 3300pF Each Driver 80 ns

tON(MIN) Minimum On-Time Tested with a Square Wave (Note 7) 180 ns

INTVCC Linear Regulator

VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTCC = 4V 4.8 5.0 5.2 VVLDO INT INTVCC Load Regulation ICC = 0 to 20mA, VEXTVCC = 4V 0.2 2.0 %

VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 100 200 mV

VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive l 4.5 4.7 V

VLDOHYS EXTVCC Hysteresis 0.2 V

Oscillator

fOSC Oscillator Frequency VFREQSET = Open (Note 8) 190 220 250 kHz

fLOW Lowest Frequency VFREQSET = 0V 120 140 160 kHz

The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.

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Efficiency vs Output Current(Figure 13)

Efficiency vs Input Voltage(Figure 13)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fHIGH Highest Frequency VFREQSET = 2.4V 280 310 360 kHz

IFREQSET FREQSET Input Current VFREQSET = 0V 2 1 A3.3V Linear Regulator

V3.3OUT 3.3V Regulator Output Voltage No Load l 3.20 3.35 3.45 V

V3.3IL 3.3V Regulator Load Regulation I3.3 = 0 to 10mA 0.5 2 %

V3.3VL 3.3V Regulator Line Regulation 6V < VIN < 30V 0.05 0.2 %

PGOOD Output

VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V

IPGOOD PGOOD Leakage Current VPGOOD = 5V 1 A

VPG PGOOD Trip Level, Either Controller VOSENSE Respect to Set Output VoltageVOSENSE Ramping NegativeVOSENSE Ramping Positive

66

7.57.5

9.59.5

%%

Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any AbsoluteMaximum Rating condition for extended periods may affect devicereliability and lifetime.

Note 2: The LTC3707E is guaranteed to meet performance specificationsfrom 0C to 85C. Specifications over the 40C to 85C operatingtemperature range are assured by design, characterization and correlationwith statistical process controls. The LTC3707I is guaranteed to meetperformance specifications over the full 40C to 85C operatingtemperature range.

Note 3: TJ is calculated from the ambient temperature TA and powerdissipation PD according to the following formula:

LTC3707EGN = TJ = TA + (PD 85C/W)

Note 4: The LTC3707 is tested in a feedback loop that ser vos VITH1, 2 to aspecified voltage and measures the resultant VOSENSE1, 2.Note 5: Dynamic supply current is higher due to the gate charge beingdelivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delaytimes are measured using 50% levels.

Note 7: The IC minimum on-time is tested under an ideal conditionwithout external power FETs. It can be different when the IC is working inan actual circuit. See Minimum On-Time Considerations in the ApplicationInformation section.

Note 8: VFREQSET pin internally tied to a 1.19V reference through alarge resistance.

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency vs Output Currentand Mode (Figure 13)

OUTPUT CURRENT (A)

0.0010

EFFICIENC

Y(%)

10

30

40

50

100

70

0.01 0.1 1

3707 G01

20

80

90

60

10

FORCEDCONTINUOUSMODE (PWM)

CONSTANTFREQUENCY(BURST DISABLE)

Burst ModeOPERATION

VIN = 15VVOUT = 5V

OUTPUT CURRENT (A)

0.001

EFFICIENCY(%)

70

80

10

3707 G02

60

500.01 0.1 1

100

90

VIN = 10V

VIN = 15V

VIN = 7V

VIN = 20V

VIN = 15VVOUT = 5V

INPUT VOLTAGE (V)

5

EFFICIENCY(%)

70

80

3707 G03

60

5015 25 30

100

VOUT = 5VIOUT = 3A

90

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.

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Supply Current vs Input Voltageand Mode (Figure 13) EXTVCC Voltage Drop

INTVCC and EXTVCC SwitchVoltage vs Temperature

Internal 5V LDO Line RegMaximum Current SenseThreshold vs Duty Factor

Maximum Current SenseThreshold vs Percent of NominalOutput Voltage (Foldback)

Maximum Current SenseThreshold vs VRUN/SS (Soft-Start)

Maximum Current Sense Thresholdvs Sense Common Mode Voltage

Current Sense Thresholdvs ITH Voltage

INPUT VOLTAGE (V)

0 50

SUPPLYCURRENT(A)

400

1000

10 20 25

3707 G04

200

800

600

15 30

BOTHCONTROLLERS ON

STANDBY

SHUTDOWN

CURRENT (mA)

0

EXTVCCVOLTAGEDROP(mV)

200

150

100

50

040

3707 G05

10 20 30

TEMPERATURE (C)

50

INTVCCANDEXTVCCSWITCHVOLTAGE(V)

4.95

5.00

5.05

25 75

3707 G06

4.90

4.85

25 0 50 100 125

4.80

4.70

4.75

INTVCC VOLTAGE

EXTVCC SWITCHOVER THRESHOLD

INPUT VOLTAGE (V)

0

4.8

4.9

5.1

15 25

3707 G07

4.7

4.6

5 10 20 30

4.5

4.4

5.0

INTVCCVOLTAGE(V)

ILOAD = 1mA

DUTY FACTOR (%)

00

VSENSE(mV)

25

50

75

20 40 60 80

3707 G08

100

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

0

VSENSE(mV)

40

50

60

100

3707 G09

30

20

025 50 75

10

80

70

VRUN/SS (V)

00

VSENSE(mV

)

20

40

60

80

1 2 3 4

3707 G10

5 6

VSENSE(CM) = 1.6V

COMMON MODE VOLTAGE (V)

0

VSENSE(mV

)

72

76

80

4

3707 G11

68

64

601 2 3 5

VITH (V)

0

VSENSE(mV

)

30

50

70

90

2

3707 G12

10

10

20

40

60

80

0

20

300.5 1 1.5 2.5

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Load Regulation VITH VS VRUN/SS SENSE Pins Total Source Current

Maximum Current SenseThreshold vs Temperature

Dropout Voltage vs Output Current(Figure 13) RUN/SS Current vs Temperature

Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13)

LOAD CURRENT (A)

0

NORMALIZEDVOUT(%)

0.2

0.1

4

3707 G13

0.3

0.41 2 3 5

0.0FCB = 0VVIN = 15VFIGURE 1

VRUN/SS (V)

00

VITH(V)

0.5

1.0

1.5

2.0

2.5

1 2 3 4

3707 G14

5 6

VOSENSE = 0.7V

VSENSE COMMON MODE VOLTAGE (V)

0

ISENSE(A)

0

3707 G15

50

1002 4

50

100

6

TEMPERATURE (C)

50 2570

VSENSE(mV)

74

80

0 50 75

3707 G17

72

78

76

25 100 125

OUTPUT CURRENT (A)

00

DROPOUTVOLTAGE(V)

1

2

3

4

0.5 1.0 1.5 2.0

3707 G18

2.5 3.0 3.5 4.0

RSENSE = 0.015

RSENSE = 0.010

VOUT = 5V

TEMPERATURE (C)

50 250

RUN/SSCURRENT(A)

0.2

0.6

0.8

1.0

75 10050

1.8

3707 G25

0.4

0 25 125

1.2

1.4

1.6

VIN = 15VVOUT = 5V

5ms/DIV 3707 G19

VRUN/SS

5V/DIV

VOUT5V/DIV

IOUT2A/DIV

VIN = 15VVOUT = 5VLOAD STEP = 0A TO 3ABurst Mode OPERATION

20s/DIV 3707 G20

VOUT200mV/DIV

IOUT2A/DIV

VIN = 15VVOUT = 5VLOAD STEP = 0A TO 3ACONTINUOUS OPERATION

20s/DIV 3707 G21

VOUT200mV/DIV

IOUT2A/DIV

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Input Source/CapacitorInstantaneous Current (Figure 13) Burst Mode Operation (Figure 13)

Constant Frequency (Burst Inhibit)Operation (Figure 13)

Current Sense Pin Input Currentvs Temperature

EXTVCC Switch Resistancevs Temperature

Oscillator Frequencyvs Temperature

Undervoltage Lockoutvs Temperature

Shutdown Latch Thresholdsvs Temperature

TEMPERATURE (C)

50 2525

CURRENTSENSEINPUTCURRENT(A)

29

35

0 50 75

3707 G26

27

33

31

25 100 125

VOUT = 5V

TEMPERATURE (C)

50 250

EXT

VCCSWITCHRESISTANCE()

4

10

0 50 75

3707 G27

2

8

6

25 100 125

TEMPERATURE (C)

50

200

250

350

25 75

3707 G28

150

100

25 0 50 100 125

50

0

300

FREQUENCY(kHz)

VFREQSET = 5V

VFREQSET = OPEN

VFREQSET = 0V

TEMPERATURE (C)

50

UNDERVOLTAGELO

CKOUT(V)

3.40

3.45

3.50

25 75

3707 G29

3.35

3.30

25 0 50 100 125

3.25

3.20

TEMPERATURE (C)

50 250

SHUTDOWNLATCHTHR

ESHOLDS(V)

0.5

1.5

2.0

2.5

75 10050

4.5

3707 G30

1.0

0 25 125

3.0

3.5

4.0 LATCH ARMING

LATCHOFF

THRESHOLD

VIN = 15VVOUT = 5VIOUT5 = IOUT3.3 = 2A

1s/DIV 3707 G22

VIN200mV/DIV

IIN2A/DIV

VSW210V/DIV

VSW110V/DIV

VIN = 15VVOUT = 5VVFCB = OPENIOUT = 20mA

10s/DIV 3707 G23

IOUT0.5A/DIV

VOUT20mV/DIV

VIN = 15VVOUT = 5VVFCB = 5VIOUT = 20mA

2s/DIV 3707 G24

IOUT0.5A/DIV

VOUT20mV/DIV

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PIN FUNCTIONS

RUN/SS1, RUN/SS2 (Pins 1, 15): Combination of soft-start,run control inputs and short-circuit detection timers. Acapacitor to ground at each of these pins sets the ramp

time to full output current. Forcing either of these pinsback below 1.0V causes the IC to shut down the circuitryrequired for that particular controller. Latchoff overcurrentprotection is also invoked via this pin as described in theApplications Information section.

SENSE1+, SENSE2+ (Pins 2, 14): The (+) Input to theDifferential Current Comparators. The ITH pin voltage andcontrolled offsets between the SENSEand SENSE+ pins inconjunction with RSENSE set the current trip threshold.

SENSE1, SENSE2 (Pins 3, 13): The () Input to the

Differential Current Comparators.

VOSENSE1, VOSENSE2 (Pins 4, 12): Receives the remotely-sensed feedback voltage for each controller from an externalresistive divider across the output.

FREQSET (Pin 5):Frequency Control Input to the Oscillator.This pin can be left open, tied to ground, tied to INTVCCor driven by an external voltage source. This pin can alsobe used with an external phase detector to build a truephase-locked loop.

STBYMD (Pin 6): Control pin that determines which cir-cuitry remains active when the controllers are shut downand/or provides a common control point to shut down bothcontrollers. See the Operation section for details.

FCB (Pin 7): Forced Continuous Control Input. This inputacts on both controllers and is normally used to regulate asecondary winding. Pulling this pin below 0.8V will forcecontinuous synchronous operation on both controllers.Do not leave this pin floating.

ITH1,ITH2(Pins 8, 11):Error Amplifier Output and SwitchingRegulator Compensation Point. Each associated channelscurrent comparator trip point increases with this controlvoltage.

SGND (Pin 9): Small Signal Ground common to bothcontrollers, must be routed separately from high currentgrounds to the common () terminals of the COUTcapacitors.

3.3VOUT (Pin 10): Output of a linear regulator capableof supplying 10mA DC with peak currents as high as50mA.

PGND (Pin 20): Driver Power Ground. Connects to thesources of bottom (synchronous) N-channel MOSFETs,anodes of the Schottky rectifiers and the () terminal(s)of CIN.

INTVCC (Pin 21): Output of the Internal 5V Linear LowDropout Regulator and the EXTVCC Switch. The driver andcontrol circuits are powered from this voltage source. Mustbe decoupled to power ground with a minimum of 4.7Ftantalum or other low ESR capacitor. The INTVCC regulatorstandby function is determined by the STBYMD pin.

EXTVCC(Pin 22):External Power Input to an Internal SwitchConnected to INTVCC. This switch closes and supplies VCCpower, bypassing the internal low dropout regulator, when-ever EXTVCC is higher than 4.7V. See EXTVCC connectionin Applications section. Do not exceed 7V on this pin.

BG1, BG2 (Pins 23, 19): High Current Gate Drives for Bot-tom (Synchronous) N-Channel MOSFETs. Voltage swingat these pins is from ground to INTVCC.

VIN (Pin 24): Main Supply Pin. A bypass capacitor shouldbe tied between this pin and the signal ground pin.

BOOST1, BOOST2 (Pins 25, 18): Bootstrapped Suppliesto the Top Side Floating Drivers. Capacitors are connectedbetween the boost and switch pins and Schottky diodes aretied between the boost and INTVCC pins. Voltage swing atthe boost pins is from INTVCC to (VIN + INTVCC).

SW1, SW2 (Pins 26, 17): Switch Node Connections toInductors. Voltage swing at these pins is from a Schottkydiode (external) voltage drop below ground to VIN.

TG1, TG2 (Pins 27, 16): High Current Gate Drives for

Top N-Channel MOSFETs. These are the outputs of float-ing drivers with a voltage swing equal to INTVCC 0.5Vsuperimposed on the switch node voltage SW.

PGOOD (Pin 28): Open-Drain Logic Output. PGOOD ispulled to ground when the voltage on either VOSENSE pinis not within 7.5% of its set point.

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FUNCTIONAL DIAGRAM

SWITCHLOGIC

+

0.8V

4.8V

5V

VIN

4.5V

BINH

CLK2

CLK1

0.18AR6

R5

+

FCB

+

+

+

+ VREF

INTERNALSUPPLY

3.3VOUT

VSEC 3V

FCB

PGOOD

EXTVCC

INTVCC

SGND

STBYMD

+

5VLDOREG

SW

SHDN

0.55V

TOP

BOOST

TG CB

CIND1

DB

PGND

BOTBG

INTVCC

INTVCC

VIN

+

CSEC

COUT

VOUT

3707 FD/F02

DSEC

RSENSE

R2

+

VOSENSE

DROPOUTDET

RUNSOFT-START

BOT

TOP ONS

R

Q

Q

OSCILLATOR

FREQSET

FCB

EA

0.86V

0.80V

OV

VFB

1.2A

6V

R1

+

+

0.74V

0.86V

VFB

+

RC

4(VFB)

RSTSHDN

RUN/SS

ITHCC

CC2

CSS

1.19V

1M

+

4(VFB)0.86V

SLOPECOMP

3mV

+

+

SENSE

SENSE+

INTVCC

30k

45k

2.4V

45k

30k

I1 I2

B

DUPLICATE FOR SECONDCONTROLLER CHANNEL

+ +

Figure 2

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OPERATION

Main Control Loop

The LTC3707 uses a constant frequency, current mode

step-down architecture with the two controller channelsoperating 180 degrees out of phase. During normaloperation, each top MOSFET is turned on when the clockfor that channel sets the RS latch, and turned off whenthe main current comparator, I1, resets the RS latch.The peak inductor current at which I1 resets the RSlatch is controlled by the voltage on the ITH pin, whichis the output of each error amplifier EA. The VOSENSE pinreceives the voltage feedback signal, which is comparedto the internal reference voltage by the EA. When the loadcurrent increases, it causes a slight decrease in VOSENSE

relative to the 0.8V reference, which in turn causes theITH voltage to increase until the average inductor currentmatches the new load current. After the top MOSFET hasturned off, the bottom MOSFET is turned on until either theinductor current starts to reverse, as indicated by currentcomparator I2, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating bootstrapcapacitor CB, which normally is recharged during each offcycle through an external diode when the top MOSFETturns off. As VIN decreases to a voltage close to VOUT,the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detectsthis and forces the top MOSFET off for about 500ns everytenth cycle to allow CB to recharge.

The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.2Acurrent source to charge soft-start capacitor CSS. WhenCSS reaches 1.5V, the main control loop is enabled with theITH voltage clamped at approximately 30% of its maximumvalue. As CSS continues to charge, the ITH pin voltage isgradually released allowing normal, full-current operation.

When both RUN/SS1 and RUN/SS2 are low, all LTC3707controller functions are shut down, and the STBYMD pindetermines if the standby 5V and 3.3V regulators arekept alive.

Low Current Operation

The FCB pin is a multifunction pin providing twofunctions: 1) an analog input to provide regulation for a

secondary winding by temporarily forcing continuousPWM operation on both controllers and 2) a logic inputto select between two modes of low current operation.

When the FCB pin voltage is below 0.800V, the controllerforces continuous PWM current mode operation. Inthis mode, the top and bottom MOSFETs are alternatelyturned on to maintain the output voltage independentof direction of inductor current. When the FCB pin isbelow VINTVCC 2V but greater than 0.80V, the controllerenters Burst Mode operation. Burst Mode operation setsa minimum output current level before inhibiting the topswitch and turns off the synchronous MOSFET(s) whenthe inductor current goes negative. This combination ofrequirements will, at low currents, force the ITH pin below

a voltage threshold that will temporarily inhibit turn-on ofboth output MOSFETs until the output voltage drops. Thereis 60mV of hysteresis in the burst comparator B tied tothe ITH pin. This hysteresis produces output signals to theMOSFETs that turn them on for several cycles, followedby a variable sleep interval depending upon the loadcurrent. The resultant output voltage ripple is held to avery small value by having the hysteretic comparatorafter the error amplifier gain block.

Constant Frequency Operation

When the FCB pin is tied to INTVCC, Burst Mode operationis disabled and the forced minimum output currentrequirement is removed. This provides constant frequency,discontinuous (preventing reverse inductor current)current operation over the widest possible output currentrange. This constant frequency operation is not as efficientas Burst Mode operation, but does provide a lower noise,constant frequency operating mode down to approximately1% of designed maximum output current. Voltage shouldnot be applied to the FCB pin prior to the application of

voltage to the VIN pin.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous currentoperation. This is the least efficient operating mode,but may be desirable in certain applications. The outputcan source or sink current in this mode. When sinkingcurrent while in forced continuous operation, current will

(Refer to Functional Diagram)

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OPERATION

be forced back into the main power supply potentiallyboosting the input supply to dangerous voltage levelsBEWARE!

Frequency Setting

The FREQSET pin provides frequency adjustment of theinternal oscillator from approximately 140kHz to 310kHz.This input is nominally biased through an internal resistorto the 1.19V reference, setting the oscillator frequency toapproximately 220kHz. This pin can be driven from an ex-ternal AC or DC signal source to control the instantaneousfrequency of the oscillator. Voltage should not be appliedto the FREQSET pin prior to the application of voltage to

the VIN pin.

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and mostother internal circuitry is derived from the INTVCCpin. Whenthe EXTVCC pin is left open, an internal 5V low dropoutlinear regulator supplies INTVCC power. If EXTVCC is takenabove 4.7V, the 5V regulator is turned off and an internalswitch is turned on connecting EXTVCC to INTVCC. Thisallows the INTVCCpower to be derived from a high efficiencyexternal source such as the output of the regulator itself

or a secondary winding, as described in the ApplicationsInformation.

Standby Mode Pin

The STBYMD pin is a three-state input that controls com-mon circuitry within the IC as follows: When the STBYMDpin is held at ground, both controller RUN/SS pins are pulledto ground providing a single control pin to shut down bothcontrollers. When the pin is left open, the internal RUN/SScurrents are enabled to charge the RUN/SS capacitor(s),allowing the turn-on of either controller and activating

necessary common internal biasing. When the STBYMDpin is taken above 2V, both internal linear regulators areturned on independent of the state on the RUN/SS pinsof the two switching regulator controllers, providing anoutput power source for wake-up circuitry. Decouple thepin with a small capacitor (0.01F) to ground if the pin isnot connected to a DC potential.

Output Overvoltage Protection

An overvoltage comparator, 0V, guards against transient

overshoots (>7.5%) as well as other more serious condi-tions that may overvoltage the output. In this case, the topMOSFET is turned off and the bottom MOSFET is turnedon until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an in-ternal MOSFET. The MOSFET turns on and pulls the pinlow when both the outputs are not within 7.5% of theirnominal output levels as determined by their resistivefeedback dividers. When both outputs meet the 7.5%

requirement, the MOSFET is turned off within 10s andthe pin is allowed to be pulled up by an external resistorto a source of up to 7V.

Foldback Current, Short-Circuit Detectionand Short-Circuit Latchoff

The RUN/SS capacitors are used initially to limit the inrushcurrent of each switching regulator. After the controllerhas been started and been given adequate time to chargeup the output capacitors and provide full load current, theRUN/SS capacitor is used in a short-circuit time-out circuit.If the output voltage falls to less than 70% of its nominaloutput voltage, the RUN/SS capacitor begins dischargingon the assumption that the output is in an overcurrentand/or short-circuit condition. If the condition lasts fora long enough period as determined by the size of theRUN/SS capacitor, the controllers will be shut down untilthe RUN/SS pin(s) voltage(s) are recycled. This built-inlatchoff can be overridden by providing a >5A pull-up ata compliance of 4.2V to the RUN/SS pin(s). This currentshortens the soft start period but also prevents net dis-charge of the RUN/SS capacitor(s) during an overcurrentand/or short-circuit condition. Foldback current limitingis also activated when the output voltage falls below70% of its nominal level whether or not the short-circuitlatchoff circuit is enabled. Even if a short is present andthe short-circuit latchoff is not enabled, a safe, low outputcurrent is provided due to internal current foldback andactual power dissipated is low due to the efficient natureof the current mode switching regulator.


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OPERATION

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC1628 and the LTC3707 are the first dual high

efficiency DC/DC controllers to bring the considerablebenefits of 2-phase operation to portable applications.Notebook computers, PDAs, handheld terminals and au-tomotive electronics will all benefit from the lower inputfiltering requirement, reduced electromagnetic interference(EMI) and increased efficiency associated with 2-phaseoperation.

Why the need for 2-phase operation? Up until the LTC1628was introduced, constant-frequency dual switching regula-tors operated both channels in phase (i.e., single-phaseoperation). This means that both switches turned on at

the same time, causing current pulses of up to twice theamplitude of those for one regulator to be drawn from theinput capacitor and battery. These large amplitude currentpulses increased the total RMS current flowing from theinput capacitor, requiring the use of more expensive inputcapacitors and increasing both EMI and losses in the inputcapacitor and battery.

With 2-phase operation, the two channels of the dual-switching regulator are operated 180 degrees out of phase.This effectively interleaves the current pulses drawn by the

switches, greatly reducing the overlap time where they addtogether. The result is a significant reduction in total RMS

input current, which in turn allows less expensive inputcapacitors to be used, reduces shielding requirements forEMI and improves real world operating efficiency.

Figure 3 compares the input waveforms for a representa-tive single-phase dual switching regulator to the LTC37072-phase dual switching regulator. An actual measurement ofthe RMS input current under these conditions shows that 2-phase operation dropped the input current from 2.53ARMSto 1.55ARMS. While this is an impressive reduction in itself,remember that the power losses are proportional to IRMS

2,meaning that the actual power wasted is reduced by a fac-tor of 2.66. The reduced input ripple voltage also meansless power is lost in the input power path, which could

include batteries, switches, trace/connector resistancesand protection circuitry. Improvements in both conductedand radiated EMI also directly accrue as a result of thereduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-tion is a function of the dual switching regulators relativeduty cycles which, in turn, are dependent upon the inputvoltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows howthe RMS input current varies for single-phase and 2-phaseoperation for 3.3V and 5V regulators over a wide inputvoltage range.


IIN(MEAS) = 2.53ARMS IIN(MEAS) = 1.55ARMS3707 F03a 3707 F03b

5V SWITCH20V/DIV

3.3V SWITCH20V/DIV

INPUT CURRENT5A/DIV

INPUT VOLTAGE500mV/DIV

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for DualSwitching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripplewith the LTC1628 2-Phase Regulator Allows Less Expensive Input Capacitors, ReducesShielding Requirements for EMI and Improves Efficiency

(a) (b)

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Figure 1 on the first page is a basic LTC3707 applicationcircuit. External component selection is driven by theload requirement, and begins with the selection of RSENSEand the inductor value. Next, the power MOSFETs andD1 are selected. Finally, CIN and COUT are selected. Thecircuit shown in Figure 1 can be configured for operationup to an input voltage of 28V (limited by the externalMOSFETs).

RSENSE Selection For Output Current

RSENSE

is chosen based on the required output current. TheLTC3707 current comparator has a maximum thresholdof 75mV/RSENSE and an input common mode range ofSGND to 1.1(INTVCC). The current comparator thresholdsets the peak of the inductor current, yielding a maximumaverage output current IMAX equal to the peak value lesshalf the peak-to-peak ripple current, IL.

Allowing a margin for variations in the LTC3707 and externalcomponent values yields:

OPERATION (Refer to Functional Diagram)

It can readily be seen that the advantages of 2-phase opera-tion are not just limited to a narrow operating range, butin fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reducethe input capacitor requirement to that for just one channeloperating at maximum current and 50% duty cycle.

A final question: If 2-phase operation offers such anadvantage over single-phase operation for dual switchingregulators, why hasnt it been done before? The answeris that, while simple in concept, it is hard to implement.Constant-frequency current mode switching regulatorsrequire an oscillator derived slope compensationsignal to allow stable operation of each regulator at over

50% duty cycle. This signal is relatively easy to derive insingle-phase dual switching regulators, but required thedevelopment of a new and proprietary technique to allow2-phase operation. In addition, isolation between the twochannels becomes more critical with 2-phase operationbecause switch transitions in one channel could potentiallydisrupt the operation of the other channel.

The LTC1628 and the LTC3707 are proof that these hurdleshave been surmounted. The new device offers unique ad-vantages for the ever-expanding number of high efficiency

power supplies required in portable electronics.

INPUT VOLTAGE (V)

0

INPUTRMSCURRENT(A)

3.0

2.5

2.0

1.5

1.0

0.5

010 20 30 40

3707 F04

SINGLE PHASEDUAL CONTROLLER

2-PHASEDUAL CONTROLLER

VO1 = 5V/3AVO2 = 3.3V/3A

Figure 4. RMS Input Current Comparison

APPLICATIONS INFORMATION

RSENSE =50mV

IMAX

Because of possible PCB noise in the current sensing loop,the AC current sensing ripple of VSENSE = I RSENSEalso needs to be checked in the design to get goodsignal-to-noise ratio. In general, for a reasonable goodPCB layout, a 15mV VSENSE voltage is recommendedas a conservative number to start with.

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due tothe internal compensation required to meet stability cri-terion for buck regulators operating at greater than 50%duty factor. A curve is provided to estimate this reductonin peak output current level depending upon the operatingduty factor.

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Selection of Operating Frequency

The LTC3707 uses a constant frequency architecture with

the frequency determined by an internal oscillator capacitor.This internal capacitor is charged by a fixed current plusan additional current that is proportional to the voltageapplied to the FREQSET pin.

A graph for the voltage applied to the FREQSET pin vsfrequency is given in Figure 5. As the operating frequencyis increased the gate charge losses will be higher, reducingefficiency (see Efficiency Considerations). The maximumswitching frequency is approximately 310kHz.

Inductor Value Calculation

The operating frequency and inductor selection are inter-related in that higher operating frequencies allow the useof smaller inductor and capacitor values. So why wouldanyone ever choose to operate at lower frequencies withlarger components? The answer is efficiency. A higherfrequency generally results in lower efficiency becauseof MOSFET gate charge losses. In addition to this basictrade-off, the effect of inductor value on ripple current andlow current operation must also be considered.

The inductor value has a direct effect on ripple current.The inductor ripple current IL decreases with higherinductance or frequency and increases with higher VIN:

IL =1

(f)(L)VOUT 1

VOUTVIN

OPERATING FREQUENCY (kHz)

120 170 220 270 320

FREQSETPINVOLTAGE(V)

3707 F05

2.5

2.0

1.5

1.0

0.5

0

Figure 5. FREQSET Pin Voltage vs Frequency

Accepting larger values of IL allows the use of lowinductances, but results in higher output voltage rippleand greater core losses. A reasonable starting point for

setting ripple current is I = 30% IOUT(MAX) or higher forgood load transient response and sufficient ripple currentsignal in the current loop. Remember, the maximum ILoccurs at the maximum input voltage.

The inductor value also has secondary effects. The tran-sition to Burst Mode operation begins when the averageinductor current required results in a peak current below25% of the current limit determined by RSENSE. Lowerinductor values (higher IL) will cause this to occur atlower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Modeoperation, lower inductance values will cause the burstfrequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor mustbe selected. High efficiency converters generally cannotafford the core loss found in low cost powdered iron cores,forcing the use of more expensive ferrite, molypermalloy,or Kool M cores. Actual core loss is independent of coresize for a fixed inductor value, but it is very dependent

on inductance selected. As inductance increases, corelosses go down. Unfortunately, increased inductancerequires more turns of wire and therefore copper losseswill increase.

Ferrite designs have very low core loss and are preferredat high switching frequencies, so design goals can con-centrate on copper loss and preventing saturation. Ferritecore material saturates hard, which means that induc-tance collapses abruptly when the peak design current isexceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Donot allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, lowloss core material for toroids, but it is more expensivethan ferrite. A reasonable compromise from the samemanufacturer is Kool M. Toroids are very space efficient,especially when you can use several layers of wire. Becausethey generally lack a bobbin, mounting is more difficult.

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However, designs for surface mount are available that donot increase the height significantly.

Power MOSFET and D1 SelectionTwo external power MOSFETs must be selected for eachcontroller with the LTC3707: One N-channel MOSFET forthe top (main) switch, and one N-channel MOSFET for thebottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTVCCvoltage. This voltage is typically 5V during start-up(see EXTVCC Pin Connection). Consequently, logic-levelthreshold MOSFETs must be used in most applications.The only exception is if low input voltage is expected

(VIN < 5V); then, sub-logic level threshold MOSFETs(VGS(TH) < 3V) should be used. Pay close attention to theBVDSS specification for the MOSFETs as well; most of thelogic level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the ONresistance RDS(ON), reverse transfer capacitance CRSS, inputvoltage and maximum output current. When the LTC3707is operating in continuous mode the duty cycles for thetop and bottom MOSFETs are given by:

Main SwitchDuty Cycle=

VOUT

VIN

Synchronous SwitchDuty Cycle =VIN VOUT

VIN

The MOSFET power dissipations at maximum outputcurrent are given by:

PMAIN =VOUTVIN

IMAX( )2

1+ ( )RDS(ON) +

k VIN( )2

IMAX( ) CRSS( ) f( )

PSYNC =VIN VOUT

VINIMAX( )

21+ ( )RDS(ON)

where is the temperature dependency of RDS(ON) and kis a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside N-channelequation includes an additional term for transition losses,

which are highest at high input voltages. For VIN < 20Vthe high current efficiency generally improves with largerMOSFETs, while for VIN > 20V the transition losses rapidly

increase to the point that the use of a higher RDS(ON)devicewith lower CRSS actually provides higher efficiency. Thesynchronous MOSFET losses are greatest at high inputvoltage when the top switch duty factor is low or duringa short-circuit when the synchronous switch is on closeto 100% of the period.

The term (1+) is generally given for a MOSFET in theform of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for lowvoltage MOSFETs. CRSS is usually specified in the MOSFET

characteristics. The constant k = 1.7 can be used to esti-mate the contributions of the two terms in the main switchdissipation equation.

The Schottky diode D1 shown in Figure 1 conducts dur-ing the dead-time between the conduction of the twopower MOSFETs. This prevents the body diode of thebottom MOSFET from turning on, storing charge duringthe dead-time and requiring a reverse recovery periodthat could cost as much as 3% in efficiency at high V IN.A 1A to 3A Schottky is generally a good compromise forboth regions of operation due to the relatively small aver-

age current. Larger diodes result in additional transitionlosses due to their larger junction capacitance. Schottkydiodes should be placed in parallel with the synchronousMOSFETs when operating in pulse-skip mode or in BurstMode operation.

CIN and COUT Selection

The selection of CIN is simplified by the multiphase ar-chitecture and its impact on the worst-case RMS currentdrawn through the input network (battery/fuse/capacitor).

It can be shown that the worst case RMS current occurswhen only one controller is operating. The controller withthe highest (VOUT)(IOUT) product needs to be used in theformula below to determine the maximum RMS currentrequirement. Increasing the output current, drawn fromthe other out-of-phase controller, will actually decrease theinput RMS ripple current from this maximum value (seeFigure 4). The out-of-phase technique typically reducesthe input capacitors RMS ripple current by a factor of

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30% to 70% when compared to a single phase powersupply solution.

The type of input capacitor, value and ESR rating haveefficiency effects that need to be considered in the selec-tion process. The capacitance value chosen should besufficient to store adequate charge to keep high peakbattery currents down. 20F to 40F is usually sufficientfor a 25W output supply operating at 200kHz. The ESR ofthe capacitor is important for capacitor power dissipationas well as overall battery efficiency. All of the power (RMSripple current ESR) not only heats up the capacitor butwastes power from the battery.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON

and switcher-rated electrolytic capacitors can be usedas input capacitors, but each has drawbacks: ceramicvoltage coefficients are very high and may have audiblepiezoelectric effects; tantalums need to be surge-rated;OS-CONs suffer from higher inductance, larger case sizeand limited surface-mount applicability; electrolyticshigher ESR and dryout possibility require several to beused. Multiphase systems allow the lowest amount ofcapacitance overall. As little as one 22F or two to three10F ceramic capacitors are an ideal choice in a 20W to50W power supply due to their extremely low ESR. Even

though the capacitance at 20V is substantially below theirrating at zero-bias, very low ESR loss makes ceramicsan ideal candidate for highest efficiency battery operatedsystems. Also consider parallel ceramic and high qualityelectrolytic capacitors as an effective means of achievingESR and bulk capacitance goals.

In continuous mode, the source current of the top N-channelMOSFET is a square wave of duty cycle VOUT/VIN. To preventlarge voltage transients, a low ESR input capacitor sized forthe maximum RMS current of one channel must be used.

The maximum RMS capacitor current is given by:

CIN RequiredIRMS IMAXVOUT VIN VOUT( )

1/2

VIN

This formula has a maximum at VIN = 2VOUT, whereIRMS = IOUT/2. This simple worst case condition is com-monly used for design because even significant deviationsdo not offer much relief. Note that capacitor manufacturers

ripple current ratings are often based on only 2000 hoursof life. This makes it advisable to further derate the capaci-tor, or to choose a capacitor rated at a higher temperature

than required. Several capacitors may also be paralleledto meet size or height requirements in the design. Alwaysconsult the manufacturer if there is any question.

The benefit of the LTC3707 multiphase can be calculated byusing the equation above for the higher power controllerand then calculating the loss that would have resulted ifboth controller channels switch on at the same time. Thetotal RMS power lost is lower when both controllers areoperating due to the interleaving of current pulses throughthe input capacitors ESR. This is why the input capacitors

requirement calculated above for the worst-case controlleris adequate for the dual controller design. Remember thatinput protection fuse resistance, battery resistance and PCboard trace resistance losses are also reduced due to thereduced peak currents in a multiphase system. The overallbenefit of a multiphase design will only be fully realizedwhen the source impedance of the power supply/batteryis included in the efficiency testing. The drains of thetwo top MOSFETS should be placed within 1cm of eachother and share a common CIN(s). Separating the drainsand CIN may produce undesirable voltage and current

resonances at VIN.The selection of COUT is driven by the required effectiveseries resistance (ESR). Typically once the ESR require-ment is satisfied the capacitance is adequate for filtering.The output ripple (VOUT) is determined by:

VOUT IL ESR+1

8fCOUT

Where f = operating frequency, COUT = output capacitance,andIL= ripple current in the inductor. The output ripple is

highest at maximum input voltage sinceIL increases withinput voltage. WithIL= 0.3IOUT(MAX) the output ripple willtypically be less than 50mV at max VIN assuming:

COUT Recommended ESR < 2 RSENSE

and COUT > 1/(8fRSENSE)

The first condition relates to the ripple current into the ESRof the output capacitance while the second term guarantees

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that the output capacitance does not significantly dischargeduring the operating frequency period due to ripple current.The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can becompensated for by using capacitors of very low ESR tomaintain the ripple voltage at or below 50mV. The ITH pinOPTI-LOOP compensation components can be optimizedto provide stable, high performance transient responseregardless of the output capacitors selected.

Manufacturers such as Nichicon, United Chemicon andSanyo can be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectriccapacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhathigher price. An additional ceramic capacitor in parallelwith OS-CON capacitors is recommended to reduce theinductance effects.

In surface mount applications multiple capacitors mayneed to be used in parallel to meet the ESR, RMS currenthandling and load step requirements of the application.Aluminum electrolytic, dry tantalum and special polymercapacitors are available in surface mount packages. Specialpolymer surface mount capacitors offer very low ESR buthave lower storage capacity per unit volume than other

capacitor types. These capacitors offer a very cost-effectiveoutput capacitor solution and are an ideal choice whencombined with a controller having high loop bandwidth.Tantalum capacitors offer the highest capacitance densityand are often used as output capacitors for switchingregulators having controlled soft-start. Several excellentsurge-tested choices are the AVX TPS, AVX TPSV orthe KEMET T510 series of surface mount tantalums,available in case heights ranging from 2mm to 4mm.Aluminum electrolytic capacitors can be used in cost-drivenapplications providing that consideration is given to ripple

current ratings, temperature and long term reliability. Atypical application will require several to many aluminumelectrolytic capacitors in parallel. A combination of theabove mentioned capacitors will often result in maximizingperformance and minimizing overall cost. Other capacitortypes include Nichicon PL series, NEC Neocap, PansonicSP and Sprague 595D series. Consult manufacturers forother specific recommendations.

INTVCC Regulator

An internal P-channel low dropout regulator produces 5V

at the INTVCC pin from the VIN supply pin. INTVCC pow-ers the drivers and internal circuitry within the LTC3707.The INTVCC pin regulator can supply a peak current of40mA and must be bypassed to ground with a minimumof 4.7F tantalum, 10F special polymer, or low ESR typeelectrolytic capacitor. A 1F ceramic capacitor placed di-rectly adjacent to the INTVCC and PGND IC pins is highlyrecommended. Good bypassing is necessary to supplythe high transient currents required by the MOSFET gatedrivers and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-mum junction temperature rating for the LTC3707 to beexceeded. The system supply current is normally dominatedby the gate charge current. Additional external loading ofthe INTVCC and 3.3V linear regulators also needs to betaken into account for the power dissipation calculations.The total INTVCC current can be supplied by either the 5Vinternal linear regulator or by the EXTVCC input pin. Whenthe voltage applied to the EXTVCC pin is less than 4.7V, allof the INTVCC current is supplied by the internal 5V linearregulator. Power dissipation for the IC in this case is high-

est: (VIN)(IINTVCC), and overall efficiency is lowered. Thegate charge current is dependent on operating frequencyas discussed in the Efficiency Considerations section.The junction temperature can be estimated by using theequations given in Note 2 of the Electrical Characteristics.For example, the LTC3707 VIN current is limited to lessthan 24mA from a 24V supply when not using the EXTVCCpin as follows:

TJ = 70C + (24mA)(24V)(95C/W) = 125C

Use of the EXTVCC input pin reduces the junction tem-

perature to:

TJ = 70C + (24mA)(5V)(95C/W) = 81C

Dissipation should be calculated to also include any addedcurrent drawn from the internal 3.3V linear regulator.To prevent maximum junction temperature from beingexceeded, the input supply current must be checkedoperating in continuous mode at maximum VIN.

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EXTVCC Connection

The LTC3707 contains an internal P-channel MOSFET

switch connected between the EXTVCC and INTVCC pins.When the voltage applied to EXTVCC rises above 4.7V,the internal regulator is turned off and the switch closes,connecting the EXTVCC pin to the INTVCC pin thereby sup-plying internal power. The switch remains closed as longas the voltage applied to EXTVCC remains above 4.5V. Thisallows the MOSFET driver and control power to be derivedfrom the output during normal operation (4.7V < VOUT (COUT )(VOUT) (104) (RSENSE)

The minimum recommended soft-start capacitor of

CSS = 0.1F will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC3707 current comparator has a maximum sensevoltage of 75mV resulting in a maximum MOSFET cur-rent of 75mV/RSENSE. The maximum value of currentlimit generally occurs with the largest VIN at the highestambient temperature, conditions that cause the highestpower dissipation in the top MOSFET.

The LTC3707 includes current foldback to help further

limit load current when the output is shorted to ground.The foldback circuit is active even when the overloadshutdown latch described above is overridden. If theoutput falls below 70% of its nominal output level, thenthe maximum sense voltage is progressively lowered from75mV to 25mV. Under short-circuit conditions with verylow duty cycles, the LTC3707 will begin cycle skipping inorder to limit the short-circuit current. In this situationthe bottom MOSFET will be dissipating most of the power

3.3V OR 5V RUN/SS

VIN INTVCC

RUN/SSD1

CSS

RSS*

CSS

RSS*

3707 F07*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

Figure 7. RUN/SS Pin Interfacing

(a) (b)

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but less than in normal operation. The short-circuit ripplecurrent is determined by the minimum on-time tON(MIN)of the LTC3707 (less than 200ns), the input voltage and

inductor value:

IL(SC) = tON(MIN) (VIN/L)

The resulting short-circuit current is:

ISC =

25mV

RSENSE+

1

2IL(SC)

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a systeminput fuse when the output voltage of the regulator risesmuch higher than nominal levels. The crowbar causes hugecurrents to flow, that blow the fuse to protect against ashorted top MOSFET if the short occurs while the control-ler is operating.

A comparator monitors the output for overvoltage con-ditions. The comparator (0V) detects overvoltage faultsgreater than 7.5% above the nominal output voltage. Whenthis condition is sensed, the top MOSFET is turned off andthe bottom MOSFET is turned on until the overvoltagecondition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and willtherefore allow a switching regulator system having a poorPC layout to function while the design is being debugged.The bottom MOSFET remains on continuously for as longas the 0V condition persists; if VOUT returns to a safe level,normal operation automatically resumes. A shorted topMOSFET will result in a high current condition which willopen the system fuse. The switching regulator will regulateproperly with a leaky top MOSFET by altering the dutycycle to accommodate the leakage.

The Standby Mode (STBYMD) Pin FunctionThe Standby Mode (STBYMD) pin provides several choicesfor start-up and standby operational modes. If the pin ispulled to ground, the RUN/SS pins for both controllersare internally pulled to ground, preventing start-up andthereby providing a single control pin for turning off bothcontrollers at once. If the pin is left open or decoupled witha capacitor to ground, the RUN/SS pins are each internallyprovided with a starting current enabling external control

for turning on each controller independently. If the pin isprovided with a current of >3A at a voltage greater than2V, both internal linear regulators (INTVCC and 3.3V) will

be on even when both controllers are shut down. In thismode, the onboard 3.3V and 5V linear regulators canprovide power to keep-alive functions such as a keyboardcontroller. This pin can also be used as a latching onand/or latching off power switch if so designed.

Frequency of Operation

The LTC3707 has an internal voltage controlled oscillator.The frequency of this oscillator can be varied over a 2 to 1range. The pin is internally self-biased at 1.19V, resulting

in a free-running frequency of approximately 220kHz. TheFREQSET pin can be grounded to lower this frequency toapproximately 140kHz or tied to the INTVCC pin to yieldapproximately 310kHz. The FREQSET pin may be drivenwith a voltage from 0 to INTVCC to fix or modulate theoscillator frequency as shown in Figure 5.

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest time durationthat the LTC3707 is capable of turning on the top MOSFET.It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low dutycycle applications may approach this minimum on-timelimit and care should be taken to ensure that

tON(MIN) 1F) supply bypass capacitors. Thedischarged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator canalter its delivery of current quickly enough to prevent thissudden step change in output voltage if the load switchresistance is low and it is driven quickly. If the ratio ofCLOAD to COUT is greater than1:50, the switch rise timeshould be controlled so that the load rise time is limitedto approximately 25 CLOAD. Thus a 10F capacitor wouldrequire a 250s rise time, limiting the charging currentto about 200mA.

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Automotive Considerations: Plugging into theCigarette Lighter

As battery-powered devices go mobile, there is a naturalinterest in plugging into the cigarette lighter in order toconserve or even recharge battery packs during opera-tion. But before you connect, be advised: you are plug-ging into the supply from hell. The main power line in anautomobile is the source of a number of nasty potentialtransients, including load-dump, reverse-battery, anddouble-battery.

Load-dump is the result of a loose battery cable. When thecable breaks connection, the field collapse in the alterna-tor can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

Figure 9. Automotive Application Protection

VIN

3707 F09

LTC3707

TRANSIENT VOLTAGESUPPRESSORGENERAL INSTRUMENT1.5KA24A

50A IPK RATING

12V

just what it says, while double-battery is a consequence oftow-truck operators finding that a 24V jump start crankscold engines faster than 12V.

The network shown in Figure 9 is the most straight for-ward approach to protect a DC/DC converter from theravages of an automotive power line. The series diodeprevents current from flowing during reverse-battery,while the transient suppressor clamps the input voltageduring load-dump. Note that the transient suppressorshould not conduct during double-battery operation, butmust still clamp the input voltage below breakdown of theconverter. Although the LTC3707 has a maximum inputvoltage of 30V, most applications will be limited to 28V

by the MOSFET BVDSS.

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Design Example

As a design example for one channel, assume V IN =

12V(nominal), VIN = 22V(max), VOUT = 2V, IMAX = 5A,and f = 300kHz.

The inductance value is chosen first based on a 30% ripplecurrent assumption. The highest value of ripple currentoccurs at the maximum input voltage. Tie the FREQSETpin to the INTVCC pin for 300kHz operation. The minimuminductance for 30% ripple current is:

IL =VOUT(f)(L)

1VOUTVIN

A 4.7H inductor will produce 25% ripple current and a3.3H will result in 36%. The peak inductor current will bethe maximum DC value plus one half the ripple current, or5.92A, for the 3.3H value. Increasing the ripple currentwill also help ensure that the minimum on-time of 200nsis not violated. The minimum on-time occurs at maximumVIN:

tON(MIN) =VOUT

VIN(MAX)f=

2V

22V(300kHz)= 303ns

The RSENSE

resistor value can be calculated by using themaximum current sense voltage specification with someaccommodation for tolerances:

RSENSE

60mV

5.92A 0.01

Since the output voltage is below 2.4V the output resistivedivider will need to be sized to not only set the outputvoltage but also to absorb the SENSE pins specified inputcurrent.

R1(MAX) = 24k 0.8V2.4V VOUT

= 24K0.8V

2.4V 1.8V

= 32k

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yieldsan output voltage of 1.816V.

The power dissipation on the top side MOSFET can beeasily estimated. Choosing a Siliconix Si4412DY resultsin; RDS(ON) = 0.042, CRSS = 100pF. At maximum inputvoltage with T(estimated) = 50C:

PMAIN =2V

22V5( )

21+ (0.005)(50C25C)[ ]

0.042( )+1.7 22V( )2

5A( ) 100pF( ) 300kHz( )= 230mW

A short-circuit to ground will result in a folded back current

of:

ISC =25mV

0.01+

1

2

200ns(22V)

3.3H

= 3.2A

with a typical value of RDS(ON) and = (0.005/C)(20) =0.1. The resulting power dissipated in the bottom MOSFETis:

PSYNC =22V2V

22V3.2A( )

21.1( ) 0.042( )

= 430mW

which is less than under full-load conditions.

CIN is chosen for an RMS current rating of at least 3A attemperature assuming only this channel is on. COUT ischosen with an ESR of 0.02 for low output ripple. Theoutput ripple in continuous mode will be highest at themaximum input voltage. The output voltage ripple due toESR is approximately:

VORIPPLE = RESR(IL) = 0.02(1.67A) = 33mVPP

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PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of theLTC3707. These items are also illustrated graphically inthe layout diagram of Figure 10. The Figure 11 illustratesthe current waveforms present in the various branchesof the 2-phase synchronous regulators operating in thecontinuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 locatedwithin 1cm of each other with a common drain connectionat CIN? Do not attempt to split the input decoupling forthe two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? Thecombined LTC3707 signal ground pin and the ground return

of CINTVCCmust return to the combined COUT() terminals.The path formed by the top N-channel MOSFET, Schottkydiode and the CIN capacitor should have short leads and

PC trace lengths. The output capacitor () terminals shouldbe connected as close as possible to the () terminalsof the input capacitor by placing the capacitors next toeach other and away from the Schottky loop describedabove.

3. Do the LTC3707 VOSENSEpins resistive dividers connectto the (+) terminals of COUT? The resistive divider mustbe connected between the (+) terminal of COUT and signalground and a small VOSENSE decoupling capacitor shouldbe as close as possible to the LTC3707 SGND pin. The R2

and R4 connections should not be along the high currentinput feeds from the input capacitor(s).

CB2

CB1

RPU

PGOOD

VPULL-UP(

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4. Are the SENSE and SENSE + leads routed together withminimum PC trace spacing? The filter capacitor betweenSENSE+ and SENSE should be as close as possible tothe IC. Ensure accurate current sensing with Kelvin con-nections at the SENSE resistor.

5. Is the INTVCC decoupling capacitor connected close tothe IC, betweenthe INTVCC and the power ground pins?This capacitor carries the MOSFET drivers current peaks.An additional 1F ceramic capacitor placed immediatelynext to the INTVCC and PGND pins can help improve noiseperformance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from theopposites channels voltage and current sensing feedbackpins. All of these nodes have very large and fast movingsignals and therefore should be kept on the output sideof the LTC3707 and occupy minimum PC trace area.

7. Use a modified star ground technique: a low imped-ance, large copper area central grounding point on the sameside of the PC board as the input and output capacitors withtie-ins for the bottom of the INTVCC decoupling capacitor,the bottom of the voltage feedback resistive divider andthe SGND pin of the IC.

RL1D1

L1SW1 RSENSE1 VOUT1

COUT1+

VIN

CIN

RIN +

RL2D2BOLD LINES INDICATEHIGH, SWITCHINGCURRENT LINES.KEEP LINES TO AMINIMUM LENGTH.

L2SW2

3707 F11

RSENSE2 VOUT2

COUT2+

Figure 11. Branch Current Waveforms

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PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in theinductor while testing the circuit. Monitor the outputswitching node (SW pin) to synchronize the oscilloscopeto the internal oscillator and probe the actual output voltageas well. Check for proper performance over the operatingvoltage and current range expected in the application. Thefrequency of operation should be maintained over the inputvoltage range down to dropout and until the output loaddrops below the low current operation thresholdtypically10% to 20% of the maximum designed current level inBurst Mode operation.

The duty cycle percentage should be maintained from cycleto cycle in a well-designed, low noise PCB implementation.Variation in the duty cycle at a subharmonic rate can sug-gest noise pickup at the current or voltage sensing inputsor inadequate loop compensation. Overcompensation ofthe loop can be used to tame a poor PC layout if regulatorbandwidth optimization is not required. Only after eachcontroller is checked for their individual performanceshould both controllers be turned on at the same time.A particularly difficult region of operation is when onecontroller channel is nearing its current comparator trip

point when the other channel is turning on its top MOSFET.This occurs around 50% duty cycle on either channel dueto the phasing of the internal clocks and may cause minorduty cycle jitter.

Short-circuit testing can be performed to verify properovercurrent latchoff, or 5A can be provided to the RUN/SSpin(s) by resistors from VIN to prevent the short-circuitlatchoff from occurring.

Reduce VIN from its nominal level to verify operationof the regulator in dropout. Check the operation of theundervoltage lockout circuit by further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-put currents or only at higher input voltages. If problemscoincide with high input voltages and low output currents,look for capacitive coupling between the BOOST, SW, TG,and possibly BG connections and the sensitive voltageand current pins. The capacitor placed across the currentsensing pins needs to be placed immediately adjacent tothe pins of the IC. This capacitor helps to minimize theeffects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered withhigh current output loading at lower input voltages, lookfor inductive coupling between CIN, Schottky and the topMOSFET components to the sensitive current and voltagesensing traces. In addition, investigate common groundpath voltage pickup between these components and theSGND pin of the IC.

An embarrassing problem, which can be missed in anotherwise properly working switching regulator, resultswhen the current sensing leads are hooked up backwards.The output voltage under this improper hookup will still

be maintained but the advantages of current mode controlwill not be realized. Compensation of the voltage loop willbe much more sensitive to component selection. Thisbehavior can be investigated by temporarily shorting outthe current sensing resistordont worry, the regulatorwill still maintain control of the output voltage.

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TYPICAL APPLICATION

Figure 12. LTC3707 High Efficiency Low Noise 5V/3A, 3.3V/5A, 12/120mA Regulator

0.1F

0.1F

4.7F

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+

22F50V

D1MBRM140T3

MBRS1100T3

D2MBRM140T3

M1 M2

M3 M4

1F10V

CMDSH-3TR

CMDSH-3TR

0.1F

10

0.01

0.015

INTVCC

3.3V

0.1F

20k1%

105k, 1%

33pF

15k

33pF

15k1000pF

1000pF

1000pF

1000pF

0.1F

20k1%

63.4k1%

RUN/SS1

SENSE1+

SENSE1

VOSENSE1

FREQSET

STBYMD

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3707

T1, 1:1.810H

L16.3H

150F, 6.3VPANASONIC SP 1F

25V

180F, 4VPANASONIC SP

GND

ON/OFF

85

123

VOUT23.3V5A; 6A PEAK

VOUT312V120mA

33F25V

VOUT15V3A; 4A PEAK

VIN7V TO28V

1628 F12

+

+

VIN: 7V TO 28VVOUT: 5V, 3A/3.3V, 6A/12V, 120mA

SWITCHING FREQUENCY = 300kHz

MI, M2, M3, M4: NDS8410A

L1: SUMIDA CEP123-6R3MC

T1: 10mH 1:1.8 DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID

LT1121

+

+

220k

100k

1M

PGOOD

100kVPULL-UP(

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

GN Package28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 .393*

(9.804 9.982)

GN28 (SSOP) 0204

1 2 3 4 5 6 7 8 9 10 11 12

.229 .244

(5.817 6.198)

.150 .157**

(3.810 3.988)

202122232425262728 19 18 17

13 14

1615

.016 .050

(0.406 1.270)

.015

.004(0.38 0.10) 45

0 8 TYP.0075 .0098

(0.19 0.25)

.0532 .0688(1.35 1.75)

.008 .012

(0.203 0.305)TYP

.004 .0098(0.102 0.249)

.0250

(0.635)BSC

.033

(0.838)REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 BSC.0165 .0015

.045 .005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASHSHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEADFLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES(MILLIMETERS)

NOTE:1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

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TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC1159 High Efficiency Synchronous Step-Down Switching Regulator 100% DC, Logic Level MOSFETs, VIN < 40V

LTC1438/LTC1439 Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulators POR, Auxiliary Regulator

LTC1438-ADJ Dual Synchronous Controller with Auxiliary Regulator POR, External Feedback Divider

LTC1538-AUX Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Auxiliary Regulator, 5V Standby

LTC1539 Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator 5V Standby, POR, Low-Battery, Aux Regulator

LTC1530 High Power Step-Down Syncrhonous DC/DC Controller in SO-8 High Efficiency 5V to 3.3V Conversion at Up to 15A

LTC1625/LTC1775 No RSENSE Current Mode Synchronous Step-Down Controller 97% Efficiency, No Sense Resistor, 16-Pin SSOP

LTC1628/LTC1628-PG Dual High Efficiency 2-Phase Synchronous Step-Down Switching Regulator Constant Frequency, 5V and 3.3V LDOs, VIN 36V

LTC1629 20A to 200A PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses AllSurface Mount Components, No Heat Sink

LTC1702 No RSENSE 2-Phase Dual Synchronous Step-Down Controller 550kHz, No Sense Resistor

LTC1703 No RSENSE 2-Phase Dual Synchronous Step-Down Controller with 5-BitMobile VID Control

Mobile Pentium III Processors, 550kHz, VIN 7V

LT1709 High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator with5-Bit VID

1.3V VOUT 3.5V, Current Mode Ensures AccurateCurrent Sharing, 3.5V VIN 36V

LTC1735 High Efficiency Synchronous Step-Down Switching Regulator Output Fault Protection, 16-Pin SSOP

LTC1736 High Efficiency Synchronous Controller with 5-Bit Mobile VID Control Output Fault Protection, 24-Pin SSOP, 3.5V VIN 36V

LTC1929 2-Phase Synchronous Controller Up to 42A, Uses All Surface Mount Components,No Heat Sink 3 5V VIN 36V

Figure 13. LTC3707 5V/4A, 3.3V/4A Regulator

0.1F

4.7F

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

+

22F50V

M1A M1B

M2A M2B

1F10V

0.1F

10

0.015

0.015

INTVCC

3.3V

0.1F

20k1%

105k1%

33pF

15k

33pF

15k

220pF

220pF

1000pF

1000pF

0.1F

20k1%

63.4k1%

RUN/SS1

SENSE1+

SENSE1

VOSENSE1

FREQSET

STBYMD

FCB

ITH1

SGND

3.3VOUT

ITH2

VOSENSE2

SENSE2

SENSE2+

PGOOD

TG1

SW1

BOOST1

VIN

BG1

EXTVCC

INTVCC

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3707

L18H

L28H

47F 6.3V

56F, 4V

GND

VOUT23.3V3A; 4A PEAK

VOUT15V3A; 4A PEAK

VIN5.2V TO28V

3707 F13

+

+

VIN: 5.2V TO 28V

VOUT: 5V, 4A/3.3V, 4A

SWITCHING FREQUENCY = 300kHz

MI, M2: FDS6982S

L1, L2: 8mH SUMIDA CEP1238R0MC

OUTPUT CAPACITORS: PANASONIC SP SERIES

27pF

27pF

0.1F

CMDSH-3TR

CMDSH-3TR

0.01F

PGOOD

VPULL-UP(

ltc3707egn

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