megacode_laptrinhvidieukhienmsp430

8/12/2019 megacode_LapTrinhViDieuKhienMSP430

1/120

1

Lp trnh hthng nhngsdng vi iu khin MSP430

(Embedded System I)

Ts. L Mnh Hi

Khoa CNTT,

H Cng nghTP HCM11/2013


2/120

2

M auI Mc ch mn hc: Cung cp kin thc vlp trnh vi iu khin TI MSP430.II. Thi gian:

30 tit l thuyt (2 tn ch) + 30 tit thc hnh (1 tn ch)III Gio trnh v ti liu tham kho MSP430 Microcontroller Basics. John H. Davies. Elsevier.

2008 (685 trang) Embedded Systems Design using the TI MSP430 Series.

Chris Nagy. Elsevier. 2003 (296trang) Introduction to Embedded Systems - A Cyber-Physical

Systems Approach, E. A. Lee and S. A. Seshia.http://LeeSeshia.org. 2011


3/120

3


4/120

4

IV. nh gi: Thi k t thc mn: Bi tlun vi 3 cu hi.

V. Gio vin: Ts. L Mnh Hi. Tel: 0985399000.

Khng gi in thoi hi hay xin im,email: [email protected],[email protected]

Website: giangvien.hutech.edu.vn GV thc hnh: Nguyn Ngc c.

0978629557


5/120

5

Ni dung chi tit

Chng 1: Cc hthng nhng v vi iu khinMSP430

Chng 2: Pht trin ng dng nhng.

Chng 3: Cc hm v ngt

Chng 4: Nhp/xut

Chng 5: Bnh thiChng 6: ADC

Chng 7: Kt ni


6/120

6

Chng 1: Cc hthng nhng vvi iu khin MSP430

Sau khi hc bi ny, sinh vin s nmc1. H thng nhng l g?

2. Cc hng pht trin h thng nhng

3. Cu trcin hnh mt vi iu khin

4. Cu trc vi iu khin MSP430G2553


7/120

7

Hthng nhng l g? Theo vi.wikipedia.org: H thng nhng (Embedded

system) l mt thut ng ch mt h thng c khnng t tr (my tnh) c nhng vo trong mtmi trng hay mt h thng m.

l cc h thng tch hp c phn cng v phnmm phc v cc bi ton chuyn dng trong nhiulnh vc cng nghip, t ng hoiu khin, quantrc v truyn tin.cim ca cc h thng nhng

l hotngnnh v c tnh nng t ng hocao.


8/120

8

Hthng nhng l g? My git

Xe hi i mi c trn 100 bxl Khong 99% chp tnh ton c ng dng trongcc hthng nhng


9/120

9


10/120

10

in thoi di ng thng minh (smartphone) TV


11/120

11

Bo Launchpad MSP430

MSP-EXP430G2 LaunchPad Experimenter Board

MSP430G2543MSP430G2553

IAR Kickstart orCode ComposerStudio Ver 5 (CCS)


12/120

12

Cc hng pht trin hthng nhng

Mt hthng iu khin tng t(trc nm1970)

Hthng my tnh s: Vi xl v vi iu khin(1970 nay)


13/120

13

Mch stch hp thp: transitor, IC 555

Mch stch hp trung bnh : CMOS 4000

Mch stch hp cao: Vi iu khin


14/120

14

Cc hng ng dng Application-specific integrated circuits (ASICs)

Chp (IC) thit kdnh ring cho mt ng dng

Field-programmable gate arrays (FPGAs) andprogrammable logic devices (PLDs)

Chp thit kc thlp trnh thay i cu to

chc nng bng cch to cc mi lin kt giacc cng bn trong chp. C hng triu cngtrong mt chp.

Microcontrollers C mt skhi rt hay c sdng cng vi

mt khi xl trung tm (CPU) .


15/120

15

Vi iu khin nh CPU xl 8 hoc 16 bt

Bnh64 KB Tc ti a : 16Mhz

Chc nng chnh: iu

khin, khng phi tnhton!

http://www.diendanti.com


16/120

16

Cu trc chung ca vi iu khin


17/120

17

Vi iu khin c 6 thnh phn cbn sau:1. Khi xl trung tm (CPU) bao gm:

Khi tnh ton shc/logic(ALU).

Khi gii m lnh v cc mch htrxlngt, ti khi ng

Cc thanh ghi bao gm thanh ghi m chngtrnh PC, con trngn xp SP, thang ghi trngthi (SR), thanh ghi to hng sCG v 12 thanhghi a nng


18/120

18

2. Bnhchng trnh: L bnhkhng mt dliu khi mt in. Trc kia l ROM, nay sdngFLASH. Chp MSP430G2553 chc 16KB3. Bnhdliu: RAM truy xut ty nhng dliu bxa khi mt in

Hin c bnhdliu khng bxa khi mtin

4. Cc cng nhp/xut: Kt ni vi cc hthngkhc

5. ng BUS dliu v BUS a ch: truyndliu v lnh gia cc khi.6. Khi xung nhp: To xung ng bcc khi


19/120

19

08 khi thng gp khc:Khi nh thi (Timer): m thi gian chnh xc. Cc vi iu

khin hin nay c t nht 2 khi ny.Khi nh thi cnh bo: L khi kim sot li chng trnh

theo thi gian. Khi ny sti khi ng chp khi chngtrnh bli .

Khi giao tip tun t: Kt ni vi cc IC khc bng cchtruyn tng bt.

Khi nhdliu khng bay hi: Lu trdliu ngay ckhimt in. Thng dng lu cu hnh thit bnha chIP

trong cc ADSL routerKhi bin i tng t- s: Cho php chuyn i tn hiutng tsang dng s.

Khi bin i s-tng t: Cho php chuyn i tn hiu

tng tsang dng s, thng dng iu khin ng cbng phng php xung s(PWM).ng hthi gian thc: Lu gigi trnm thng ngy.Bnp v chy chng trnh: Cho php np chng trnh t

my tnh vo bnhchng trnh


20/120

20

Cu trc Harvard v von Neumann

MSP 430 c cu trc von Neumann


21/120

21

Cu hi

Hy k tn mt vi thit bdn dng l hthng nhng?

Cc thnh phn cbn ca mt vi iu

khin? Cc khi htr thng gp mt VK?

Skhc bit gia cu trc Harvard v vonNeumann ?


22/120

22

Bi 2: Cu trc vi iu khinMSP430G2553

Cc chn VK MSP430G2553 Cc khi chc nng

Tchc bnh

Khi xl trung tm (CPU) Bto xung nhp

Ngt v ti khi ng

Cc ti liu chnh thng


23/120

23

Cc chn VK MSP430G2553

Chn ra: 20 chn tvnha PDIP Phn ln cc chn c nhiu chc nng.

V dchn s3 c 5 chc nng

Cc ng dng ti mi thi im chyu cumi chn thc hin mt chc nng =>

khng bmu thun


24/120

24


25/120

25

M tcc chn

VCC( chn 1) VSS (chn 20) dng cp ngun3,3V cho chp. Ngun c thdao ng trongkhong 1,8V 3,6 V

P1.0P1.7, P2.0, and P2.7 l 2 cng nhp xut s.Mi cng 8 chn (8 bt), gi tt l P1 v P2.

Cc khi chc nng cng sdng cc chn nykhi cn nhcu hnh thanh ghi chn khi P1SEL

v P2SEL.


26/120

26

Cc khi chc nng MSP430G2553


27/120

M tcc khi chc nng

27

Cc khi cbn: CPU, Xung nhp, Flash, RAM,Ports,v Bus. Cc khi b xung:

Khi np chng trnh: JTAG : 4 dy v 2 dy Khi bini tng t - s ADC. Khi bo v st p (Brownout Protection) Khi so snh p (Compare A+)

Khing h canh gc (WDT) 2 khinh thi loi A (Timer0_A3 v Timer_A3) 2 khi giao tip tun t (USCI A0 v USCI B0)


28/120

28

Bnh

Bnhl cc thanh ghi 8 bt, tchc thnhcc nh,

a ch nh16 bit t 0x0000 ti 0xFFFF

Bus dliu 16 bit c thtruyn 16 bt hoc8 bt.


29/120

29

Bus a chv cc nh


30/120

30

Tht nh

Little-endian ordering: Khi dliu c trn1 byte th byte gi trthp nm vtr di,byte gi trcao nm bn trn trong b

nh. Dng MSP430 c thtny. Big-endian ordering: Byte gi trthp nm

vtr cao. Mt schp ca Motorola,Freescale HCS08 c cu trc ny.


31/120

31

Tchc bnhT chc b nhca MSP430G2553 gm cc thnh phn sau Thanh ghi chc nng chuyn dng: Cc thanh ghi ca cc

khi c c hc nng xcnh trc. V d cc thanh ghi PC, SP,SR, CG ca CPU, thanh ghi P1REN, P1DIR ca P1...

Cc thanh ghia nng ca CPU v cc thit b ngoi vi, nhcc thanh ghi R4-R15 ca CPU, P1IN, P1OUT ca P1.

Cc thanh ghi 8 bt Cc thanh ghi 16 bt Random access memory (RAM): Cc thanh ghit trong

khi RAM ca ch t 0x0200 v ch c 256/512 Bytes

Bootstrap loader : L phn b nhkhng b xa cha chngtrnh kt ni my tnh qua cng COM ca TI


32/120

32

Bnhdliu khng bay hi (Information

memory): L 256 Byte flash, cho php lu ccthng tin quan trng v khng bmt khi mt in. Bnhchng trnh (Code memory): L bnh

chc (ROM) v cha chng trnh c np t

my tnh xung. Sau khi np v khi ng, chngtrnh ny sc c vo CPU thc thi . Chphin nay c t2KB-16KB.

Interrupt and reset vectors: L phn bnhchacc a chca cc hm xl ngt v ti khi ng.


33/120

33


34/120

34

Khi xl trung tm (CPU)

Chc nng: Khi CPU thc thi cc lnh ct trongbnhchng trnh. Cc lnh c c tun tvthc thi nu khng gp cc lnh rnhnh hoc xl ngt

Cu to: Gm mt khi tnh ton ALU 16 bt,mch gii m lnh v 16 thanh ghi.

Tn sti a (cng l tc ) do xung nhpMCLK to l 16MHz.


35/120

CPU

35


36/120

36


37/120

37

Cc thanh ghi ca CPU Thanh ghi m chng trnh (Program counter PC): Chaa chlnh ktip cn thc hin. PC tng tng 2 sau mixung nhp, ngoi trc lnh rnhnh hoc gi hm

Con tr ngn xp (Stack pointer- SP): Trn vng nhRAM dng lm ngn xp. Khi mt hm c gi, PC v SRc ct vo ngn xp v khi thc hin xong hm, cc gi trny c trli PC v SR tip tc oc6ng vic ang thc hind

Thanh ghi trng thi (Status register SR): Cha cc ctrangthi. Cc bt trng thi hay c dng l C, Z, N, v V. Ngoira c mt sbt tt xung nhp nhCPUOFF (tt MCLK)

Thanh ghi hng s(Constant generator) Dng to ra mt shng sthng gp

12 thanh ghi a nng : l cc thanh ghi dng lu thng tintrung gian. Cc thanh ghi c tc tru cp tng ng CPU


38/120

38

Bto xung nhp

Xung nhp l thit bkhng ththiu ca cc hthng s Linh kin thng dng to xung nhp l thch anh c th

to dao ng khong vi MHz cho chp (max = 16MHz) Tuy nhin khi chy tc cao, chp tiu tn nhiu in. Cc

hthng di ng cn tit kim pin nn mt sbphn chchy tn sthp stit kim v tng thi gian sdng pin.Bto xung nhp cn a dng ha cc chhot ng caVK.

Nhiu ng dng nhng phn ln thi gian trng thi ng(cng sut thp)-> Cn tt xung nhp khi c th. Khi c skin ngt, CPU sc cp xung ng bli hot ng.

.


39/120

39

Bto xung nhp


40/120

40

Bto xung thp tn bng thch anh LFXT1: C thtocc xung nhp tvi chc KHz ti 1 MHz vi chnh xccao.

Bto xung cao tn bng thch anh- XT2: Ging LFXT1ngoi trtn scao hn (8-16MHz)

Bto xung tn sthp VLO vi chnh xc thp. CcVK c thto xung nhp tn sthp m khng cn thchanh. Dng VLO nu cn tit kim nng lng (ko di thigian sdng gia hai ln sc pin)

Bto xung iu khin kthut s(DCO): To cc xungnhp tn scao (8-10MHz) m khng dng thch anh. CcVK sdng DCO trong giai on u khi khi ng

(khong 1 giy) .


41/120

41

Kim sot cc xung nhp thng qua thanh ghi

trng thi (SR)

CPUOFF kha MCLK, v dng CPU cng nhcc khi no dng MCLK ng b

SCG1 kha SMCLK v cc khi dng MCLK

ng b SCG0 kha DCO

OSCOFF kha VLO v LFXT1.


42/120

42

Cc loi xung nhp

Master clock, MCLK, sdng cho CPUv mt s khi tc cao (1-16MHz).

Subsystem master clock, SMCLK, dng

cho cc cc khi tc trung bnh (1MHz) Auxiliary clock, ACLK, Dng cho cc

khi tc thp (32KHz).


43/120

43

Khi nim Ngt v ti khi ng Ngt (Interrupts): L mt skin gy bi phn cng , mc

d c ci t bng phn mm) v thng cn c xlngay lp tc. Khi xy ra mt ngt, VK dng chng trnh

ang thc thi, ct cc thng tin/ trang thi hin ti (PC, SR)chuyn sang chng trnh xl ngt (ISR) ngay lp tc.Sau khi xl ngt xong, VK quay li thc hin tip cngvic ang thc hin trc. Nhvy chng trnh xl ngtc gi bi phn cng chkhng phi phn mm.

Ti khi ng (Resets): c to bi phn cng, thngc dng khi c skin bt thng ngu hi khin VKkhng thtip tc cng vic. Thng thng ng hcanh gcsti khi ng VK sau mt khong thi gian nht nhnu khng c can thip kp thi. Ti khi ng gip hthng vo trng thi n nh


44/120

44

Cu hi

Lit k cc thanh ghi CPU Cc ngun xung v cc loi xung ca VK TIMSP430G2553?

Ngt l g, ti sao hthng nhng cn cchngt?


45/120

45

Bi tip

Mi trng pht trin ng dng Chng trnh n gin u tin


46/120

46

Bi 3: Mi trng pht trin ngng dngSau khi hc xong SV cn nmc:1. Cc cng c h trpht trinng dng2. Ngn nglp trnh nhng C

3. Truy cp v gri4. Bo Launchpad MSP430 v cc chngtrnh bt ttn LED

C ht t i d


47/120

47

Cc cng cpht trin ng dng Bson CT (Editor): Cho php vit CT v kim tra c php

tc th Bin dch (compiler): Chng trnh chuyn m C sang m

my, c khnng d li

Gn a ch(Linker): Phi hp cc thvin v cc hm, gna ch bnh(khi np vo VK khng bnhm) Bm phng (Stand-alone simulator): Chng trnh

phng to hot ng ca VK, thay cho chp tht.

Embedded emulator/debugger: Thit bcho php np tnglnh tmy tnh xung VK gri Bnp trc tip (In-circuit emulator): Thit bgri cho

php VK chay tng lnh ttrn my tnh. Gi khong

1000$ Chng trnh np (Flash programmer): L phn mmmin ph ca TI dng np chng trnh tmy tnh vo bnhchng trnh ca VK.


48/120

48

Cc phn mm thng dng

IAR EmbeddedWorkbench. Phn mm min phcho SV.

http://www.iar.com

Code Composer StudioPhn mm min ph cho SV : 16KB chng trnh


49/120

49

The C Programming Languageif ((P1IN & BIT3) == 0)// Kim tra chn s3 Port1 c bng 0?{

P1OUT = 0x01; //cp ra port 1 gi tr 0b00000001}else

{

P1OUT = 0x00; //cp ra port 1 gi tr0b00000000}

H


50/120

50

Hp ngV d:

mov.w #WDTPW|WDTHOLD ,& WDTCTL

Sinh vin shc lp trnh hp ngnu thnh tho lp trnh bng C

B th h h


51/120

51

Bo thc hnh

The TI MSP430G2553 Launchpad Board.

Mch np

VK

2 LED

Cngtc S2

Cng tcS1


52/120

52

Cc chng trnh mu Bt /tt cc n LED c trng thi cng tc S2 Tng bt tt n dng hm gichm Automatic Control: Use of Subroutines Automatic Control: Flashing a Light by Polling

Timer_A Header Files and Issues Brushed under the

Carpet


53/120

53


54/120

54

Bt tt LED


55/120

55

Bt tt cc n LED

#include // Specific devicevoid main (void)

{WDTCTL = WDTPW | WDTHOLD;// dng watchdog timerP1DIR = 0x41;// t cc chn P1.0 v P1.6 l OUTPUT:0b01000001P1OUT = 0x41;// chai led cng sngfor (;;) {// Loop forever ...}// ... doing nothing}

Hy sa li chuong trnh Led 1 sng , led 2 tt

c trng thi cng tc


56/120

56

c trng thi cng tc

Nu cng tc S2 h(m) in p chn P1.3 s ln 1 (3,3v )

Nu cng tc S2 ng : in p trn P1.3 s xung 0 (0v)

#include // Specific device


57/120

57

#define LED1 BIT0

#define LED2 BIT6#define S2 BIT3

void main (void)

{

WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timerP1DIR = LED1|LED2; // Set pin with LED1 and LED2 to output

P1OUT = LED1|LED2; // bat LED1 va LED2 sang

P1REN |= S2; //su dung dien tro keo len/xuong, chi dung voi Launchpad v1.5

P1OUT |= S2; //dien tro keo len, sau lenh nay, S2 thuong xuyen cao (1)while(1) { // Loop forever

if ((P1IN & S2) == 0)

P1OUT |= LED1; // Yes: bat LED1

else

P1OUT &= ~ LED1; // No: tt LED1, LED2 khng thay doi

}

}

Hy vit CT bt tt LED2 bng cng tc S2. LED1 khng thay i


58/120

58

Chp n bng hm Delay()

Chng trnh tip theo schp n LED1(sng/tt) vi chu k1 giy. Nhvy thigian sng/tt l 0,5 s


59/120

59

while(1){// Loop foreverfor (LoopCtr = 0; LoopCtr < DELAYLOOPS; ++ LoopCtr) {}// Empty delay loopP1OUT = LED1|LED2;// Toggle LEDs}

}


60/120

60

Tng chp n: SdngtimerA

Sdng vng lp l gii php n ginnhng khng chnh xc: khi xy ra mt skin ngt, vng lp sbko di.

on chng trnh sau sbt tt n theotimer.

Timer sc trnh by phn sau


61/120

61

TimerA


62/120


63/120

63

Quizzes Cc phng php chp mt n LED?


64/120

64

Chng tip theo

Hm, ngt v cc chtit kim nnglng


65/120

65

Bi 4: Hm, ngt v chtit kimnng lng

1. Hm v cc bc thc thi khi gi hm2. Ngt v chng trnh phc vngt3. Cc bc thc thi khi xy ra mt ngt4. Cc chtit kim nng lng

Hm


66/120

66

Hm

Hm l cch vit chng trnh thnh cc m unnh. Vic to chng trnh tcc m un khin

chng trnh trnn r rng, dvit, dkim thvc thdng nhiu ln Mt khi hm c vit, c thng gi thnh th

vin sdng khi cn (thvin ng) Cc chng trnh nhng vit bng ngn ngcthng c cc hm di khng qu 30 dng lnh


67/120

67

Cc bc thc thi khi gi hm

Cc thng tin ca chng trnh ang thc thi cct vo ngn xp

a chca chng trnh mi c lu vo PC.Chng trnh mi c thc hin cho ti khi gplnh return.

Cc thng tin ca chng trnh cc np li tngn xp. a chlnh chng trnh ccn tiptc thc hin c np vo PC v CPU stip tcchng trnh c


68/120

68

Ngt Ngt l cchdng mt chng trnh ang chy

thc hin mt chng trnh khc khi xy ra mt skin do phn cng gy ra.

Ngt c dng khi Mt skin khn cp cn c p ng tc thi.

Cc skin rt chm.

Chuyn CPU tchngsang tch cc.

Gi hiu hnh


69/120


70/120

70

Cngt

Mi ngt c mt cngt ring, chthrng cskin cn xl gp. Chng hn Timer A c cngt TAIFG CTAIFG stng bt ln khi TARv0. Khi cngt bt ln, chng trnh xl ngt

tng ng sc gi, trtrng hp bche. Chng trnh xl mt ngt chc thc thi khi

ngt ny khng bche bi bit GIE cho php ngt

ton cc. Chng trnh chnh phi bt bt GIE (thucthanh ghi SR) cchngt c php thc hin


71/120

71

Vector ngt Vector ngt l vng nhcao trong bnhMSP430.

Vng ny cha cc a chca cc ISR. Khi GIE caov mt cngt bt ln, a chca ISR tng ng sc np tIV vo PC.

Mi ngt c mt thtu tin. Nu 2 ngt xy rang thi, th ngt c u tin cao hn sc thcthi. Thtu tin cao cao th vtr ISR trong IV cngcao.

Cc bc thc thi khi mt ISR c gi


72/120

72

Cc bc thc thi khi mt ISR c gi

1. Nu CPU ang thc hin mt lnh Lnh cn c hon tt.Nu CPU ang ng, xung MCLK c cp a CPU vchtch cc.

2. Ct PC vo ngn xp.3. Ct SR vo ngn xp.4. Chn IRS c u tin cao nht5. Xa cngt ca ISR c chn.6. Xa SR.7. t a chca ISR tIV vo PC.


73/120

73

chm

chm l thi gian tlc xy ra skinti khi chng trnh xl ngt c btu.

Trong trng hp CPU ang thc hin d1lnh, th CPU scn mt nhp hon tt vsu nhp thc hin su bc cn li trc

khi bt u ISR.


74/120

74

Khai bo ISR

Interrupt Service Routines in C#pragma vector = TIMERA0_VECTOR

__interrupt void TA0_ISR (void)

void main (void){WDTCTL = WDTPW|WDTHOLD;// Stop watchdog timer


75/120

75

P2OUT = LED1;// Preload LED1 on , LED2 offP2DIR = LED1|LED2;// Set pins with LED1 ,2 to outputTACCR0 = 49999;// Upper limit of count for TARTACCTL0 = CCIE;// Enable interrupts on Compare 0TACTL = MC_1|ID_3|TASSEL_2|TACLR;// Set up and start Timer A// "Up to CCR0" mode , divide clock by 8, clock from SMCLK , clear timer__enable_interrupt ();// Enable interrupts (intrinsic)for (;;) {// Loop forever doing nothing}// Interrupts do the work

}// ----------------------------------------------------------------------// Interrupt service routine for Timer A channel 0

#pragma vector = TIMERA0_VECTOR__interrupt void TA0_ISR (void)

{P2OUT = LED1|LED2;// Toggle LEDs}


76/120

76

Ngt khng che

C mt sngt m cGIE khng che cl Li bto dao ng OFIFG. Tranh chp bnhACCVIFG. Chn RST ba xung thp


77/120


78/120

78

QuizzesV sao Ngt li quan trng vi HTN?

Cngt lm g?

Bt GIE l g?


79/120

79

Bi sau? Cng nhp xut s


80/120

80

Bi 5: Cng nhp xut s

1. Cu trc cng nhp xut s (IO Port)

2. Cc thanh ghi ca IO3. Chng di4. Ma tr n bn phm

5. Li LED v LED 7 on6. LCD


81/120

81

Cng nhp xut s


82/120

82

Nhp xut thng dng nht l cc tn

hiu svi 2 gi tr0/1(0/3,3,V) Chng trnh v d sdng PORT 1li LED

.


83/120

83

Cng nhp xut s Cc chp MSP430 c thc t10-80 chn IO s. Mc d l chn nhp xut s, cc chn cn c dng

cho cc khi khc nhTimer, ADC Khi ti khing cc chn u l IO s

Chng hn chn P1.0 cn c dng lm TACLK


84/120

84


85/120

Cc thanh ghi ca P1


86/120

86

Port P1 direction, P1DIR: xc nh hng truyn dliu. Nubt i =0, chn P1.i sl INPUT, nu bt i=1, chn P1.i slOUTPUT . Khi khi ng cc bt P1DIR c gi tr0

Port P1 resistor enable, P1REN: Bt mt bt ca thanh ghi nyln 1 skich hot in trko ln hoc ko xung ti chn tngng.Port P1 selection, P1SEL: Chn chn tng ng l chn nhp

xut s(0 gi thmc nhin khi khi ng) hoc c chc nngkhc (1).

Digital Input and Output

P P1 i bl P1IE


87/120

87

Port P1 interrupt enable, P1IE: Cho php ngt trn chn tngng nu bt ln 1, cm ngt nu bt tng ng l 0 Port P1 interrupt edge select, P1IES: chn cnh ln to ngt

nu bt tng ng l 0, hoc cnh xung nu l 1. Thanh ghi ny

chc hiu lc nu thanh ghi P1IE bt Port P1 interrupt flag, P1IFG: L thanh ghi cha cc cngt .Khi mt chn c bt cho php ngt v c sthay i tn hiung nhthanh ghi P1IES t th c ngt tu7ong ng chn nybt ln. Nu GIE bt th ISR sc thc thi

Q b h


88/120

88

Qut ma trn bn phm

Khi snt nhn kh ln, schn chp dngiu kin cc cng tc sln.

C thgim schn VDK bn ma trn bn

phm


89/120


90/120

90

Qut bn phm1. Cp 011 cho X1X2X3 c Y1Y2Y3Y4 kim

tra cc nt 1, 4, 7, or *. Cc nt khc s khnglm thayi Y1-Y4 v X2,X3 c gi tr 1

2. Cp 101 cho X1X2X3 c Y1Y2Y3Y4 kim

tra cc nt 2, 5, 8, or 0.3. Cp 110 cho X1X2X3 c Y1Y2Y3Y4 kimtra cc nt 3, 6, 9, or #.


91/120

91

LED 7 on


92/120

92

Bi tip theo1. Cc loi Timer thng gp

2. Watchdog Timer3. Timer A

Bi 6: B nh thi


93/120

93

Bi 6: Bnh thi

1. Cc loi timer

2. Watchdog timer3. Timer A


94/120

94

Cc loi Bnh thiW t hd ti h h i hi b d


95/120

95

Watchdog timer: ng hcanh gc : c trong mi thit bdngMSP430. Chc nng chnh l chng li chng trinh nhng c thsdng nhmt bm thi gian chnh xc.Timer_A: C trong mi thit b. Loi Timer A c 3 knh v l thit

bnh thi n gin nht. Timer Ac thm thi gian, o tn shoc m cc skin lpTimer_B: Chc trong mt schp ln. y l cu trc mrng caTimer A vi sknh ln n 7 , c sdng to cc xung PWMiu khin ng cTimer Basic1: Chc trong mt schp MSP430F4XX.Real time clock: Chc trong mt schp MSP430 ln

Watchdog Timer (WDT)


96/120

96

Chc nng chnh: chng li chng trnh nhlpqun, treo VK

WDT c mt thanh ghi m ln WDTCNT v khi tgii hn trn (65535) n s khi ng li VK.

Chng trnh c vit phi nh kxa thanh ghim ln ca WDT trc khi t gii hn. Nu khnghthng sbreset.

Tuy nhin hot ng ca WDT c cu hnh bithanh ghi iu khin 16-bit WDTCTL. Bt btWDTHOLT sngng hot ng ca WDT


97/120

97

WDT lun sdng xung nhp DCO 1MHz. Khi hot ng,bt WDTCNTCL bt ln 1 sxa thanh ghi WDTCNT

// Watchdog config: active , ACLK /32768 -> 1s interval; clear counter

#define WDTCONFIG (WDTCNTCL|WDTSSEL)// Include settings for _RST/NMI pin here as well

// ----------------------------------------------------------------------


98/120

98

//

void main (void){WDTCTL = WDTPW | WDTCONFIG;// Configure and clear watchdog

P2DIR = BIT3 | BIT4;// Set pins with LEDs to outputP2OUT = BIT3 | BIT4;// LEDs off (active low)for (;;) {// Loop foreverLED2 = IFG1_bit.WDTIFG;// LED2 shows state of WDTIFGif (B1 == 1) {// Button upLED1 = 1;// LED1 off} else {// Button downWDTCTL = WDTPW | WDTCONFIG;// Feed/pet/kick/clear watchdogLED1 = 0;// LED1 on

}}}

Sdng WDT nhmt b h thi


99/120

99

nh thi Nu khng dng kim tra li chng

trnh, WDT c thc sdng nhmtbnh thi .

Bt bt WDTTMSEL trong thanh ghiWDTCTL st WDT vo chm, tuynhin khi t gii hn th WDTIFG bt lnm khng khi ng li VK

Vic c WDTCNT cho bit thi gian xy mt skin

Timer A


100/120

100

Timer_A

L bnh thi a nng thng dng, c mt trong mi chp

MSP430. Bnh thi gm 2 khi ln Timer block: L khi li vi thanh ghi TAR 16 bt, khi

chn xung nhp v khi chia tn lm chm. Khi TARkhng c tn hiu ra nhng c thbt cTAIFG khi TARv0

Capture/compare channels: L khi bt tn hiu v sosnh, c 3 khi c lp vi cc chs0,1 v 2. Khi ny

gm 0 khi con nhsau

Khi bt tn hiu Capture :Nhn tn hiu cn m tbnngoi

Khi so snh Compare Gm thanh ghi TACCR0 (hoc1 2) t hi h t b h


101/120

101

p Gm thanh ghi TACCR0 (hoc1,2) m stn hiu hoc c t bng phn mm.

Khi to ngt : bt cCCIFG khi TAR v TACCR bng

nhau. Khi ly mu Sample to tn hiu so snh .


102/120

102

Cc ch nh thi


103/120

103


104/120


105/120

105

Hthng nhng

Ts. L Mnh Hi

Khoa CNTT,

H Kthut Cng nghTP HCM

Embedded Systems

Chapter 10 : Communication


106/120

106

p

1. Communication Peripherals in the MSP430

2. Serial Peripheral Interface3. SPI with the USI

4. SPI with the USCI

5. Inter-integrated Circuit Bus

6. A Simple IC Master with the USCI_B0

7. A Simple IC Slave with the USI on a F2013


107/120

107

Communication Peripherals in the

MSP430 The universal serial interface (USI) is a lightweight module, which


108/120

108

S 30The universal serial interface (USI) is a lightweight module, whichis included in the small F20x2 and F20x3 devices. For a start, ithandles only synchronous communicationSPI and IC.

Universal Serial Communication Interfacelarger devices in the MSP430F2xx and MSP430F4xx families containone or more universal serial communication interface (USCI)

modules. The hardware handles almost all aspects of thecommunication, unlike the USI, so the software needs only to providethe data to transmit and store the received data in normal operation.Typically this requires only a couple of small interrupt service

routines. Universal Synchronous/Asynchronous Receiver/Transmitter

(USART) is an older module, which has been superseded by the

USCI.


109/120

109

Serial Peripheral Interface The serial peripheral interface was introduced by


110/120

110

p p yMotorola and is the simplest synchronouscommunication protocol in general use.

The only problem is that it is not a fixed standard likeIC. There are plenty of options within standard SPIand innumerable variations that go beyond this.


111/120

The main pins are labeled SOMI, SIMO, and CLK (2 USCI)


112/120

112

SPI block in USCI


113/120

113

SPI operationThere are separate shift registers for transmitting and receiving


114/120

114

Moreover, these registers are double-buffered and the user has nodirect access to the shift registers themselves.

This means that a byte is moved from the receive shift register toRXBUF as soon as reception is complete, which leaves the shiftregister ready to accept the next transfer.Similarly, a byte written to TXBUF remains in its buffer until the

previous byte has been transmitted, at which point it is moved to thetransmit shift register.This relaxes considerably the constraints on handling interrupts inthe USI, where the shift register must be read and updated rapidlybetween transfers. Although there are separate registers,reception and transmission are not independent because of thenature of SPI.

Read an examples C code for SPI communication

For Master

msp430g2xx3_uscia0_spi_09.cAnd for Slave


115/120

115

msp430g2xx3_uscia0_spi_10.c

Inter-integrated Circuit Bus The IC bus was introduced by Philips (now NXP)


116/120

116

g The I C bus was introduced by Philips (now NXP)

Semiconductors. It was widely adopted and has becomeeven more popular since its patents expired in 2006. It is atrue bus, unlike SPI, with a specification and user manualthat can be downloaded from NXP.

Revision 03 of the user manual is document UM10204,

dated June 19, 2007. It is clearly written and a lot easier toread than you might expect. The IC bus uses only two,bidirectional lines:

Serial data (SDA).

Serial clock (SCL).

Structure


117/120

117

Operation: Read from page 534 -542


118/120

n tp Hthng nhng

1. Cu trc tng thca vi iu khin2. Skhi ca chp TI MSP430G25533. BnhMSP430G2553: Phn bvtr bnhv

ngha tng vng nh4. Cu to CPU v ngha cc thanh ghi trong CPU


119/120

5. Cc loi xung nhp (clock) v cc chhot ng6. Hm v cc bc thc hin khi gi mt hm7. Khi nim ngt v chng trnh phc vngt8. Cc bc thc thi khi thc hin mt ngt.9. Cc chcng sut thp.10. Cc cng nhp xut s(Digital Input and Output).11. Qut ma trn bn phm. Chng di12. Cc loi LCD. Schn kt ni theo chun

HD44780

13. Cc loi timer. Cu trc v hot ng ca WDT14. Cu trc v cc chhot ng ca TimerA015. Kt ni Serial Peripheral Interface (SPI). Cu trc

v hot ng.

16. Kt ni Inter-integrated Circuit Bus (I2C).


120/120

megacode_laptrinhvidieukhienmsp430

Documents