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Using Cadence NC-Verilog or Verilog-XL Simulator

A brief tutorial is presented here to get you started on using the Cadence NC-Verilog orVerilog-XL simulator on a Unix operating system. The command name for Verilog XL is!erilog"# and the command name for NC Verilog is nc!erilog". Any $here the

Unix%Linux command !erilog" is used belo$# it can be substituted by nc!erilog".

Electronic Design Automation (EDA) Tools at NPUN&U electronics lab offers a complete set of '(A tools for A)*C and +&,A%C&L(designs. The &C !ersion of '(A tools are typically installed locally on indi!idualmachines and the UN*X%Linux !ersion of '(A tools are all installed on a Unix%Linuxser!er for easy access. ost tools offer both ,U* !ersion and A)C** !ersion of userinterface. *f you need to use the ,U* !ersion# you need direct access to a Unix%Linux$orstation or X-$indo$ soft$are such as /eflection or Xmanager. *f you use A)C**!ersion of user interface# you can remote login to the system from home or from anyother computers on the N&U computer net$or.

EDA tools organization on LinuAll '(A tools on Linux are installed at the follo$ing location0!ee!tools!

All setup files are located at0!ee!setu"!

Login to NPU Uni!Linu Net#or$'!ery registered student should ha!e a Unix%Linux account on the N&U Unix%Linuxnet$or. The account name is typically posted the first trimester you register. *f you arenot next to a Unix%Linux $orstation# you may use the X" anager program to connectto a Unix%Linux machine. 1ou may $ant to choose a machine $ith fe$er people andsmaller load.

After successfully logging in the system# do the follo$ing0

% cd

% mkdir verilog_demo

% cd verilog_demo

2here the 3" indicates the Unix prompt. After typing in the abo!e commands# youha!e created a directory called !erilog4demo" in your home directory.

Creating t%e Design &ilesTypically# you $ould enter your design using a text editor on the Unix. T$o files $ill beneeded for this tutorial. 5ne is the design itself $hich contains the beha!ior description

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for a 6-bit full adder. The other file contains all the input !ectors for running thesimulation $hich is called fixture.!.

The follo$ing is the content for the file adder6.!0

module adder6 9a# b# ci# s# co:;input ? a# b;input ci;output ? s;output co;

assign @co# s B a b ci;

endmodule

The follo$ing is the content for the file fixture.!0

module fixture;reg ? pa# pb;reg pci;$ire ? obs4s;$ire obs4co;

adder6 dut 9.a9pa:# .b9pb:# .ci9pci:# .s9obs4s:# .co9obs4co::;

initial begin Ddumpfile9adder6.!cd":; Ddump!ars98#pa#pb#pci# obs4s# obs4co:; Dmonitor9Dtime# aB3b bB3b ciB3b coB3b sumB3b"# pa# pb# pci# obs4co# obs4s:;end

initial begin E8> pa B >; pb B >; pci B >; E8> pa B 6; pb B F; pci B 8; E8> pa B G; pb B H; pci B >; E8> pa B =; pb B F; pci B 8; E8> pa B >; pb B I; pci B >; E8> pa B =; pb B F; pci B 8; E8> pa B H; pb B H; pci B 8; E8> pa B =; pb B 8; pci B 8;endendmodule

*f you are not familiar $ith Unix system# you may copy the t$o files into your $oringdirectory using the follo$ing commands0

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% cp /ee/demo/npu/ee461/adder4.v .

% cp /ee/demo/npu/ee461/fixture.v .

*n the pre!ious commands# the 'at the end of the command indicates that you $ant to

same file names. Use the ls" command to see a list of files in your $oring directory.

% ls

*f you $ant to !ie$ the content of a file# use the more" or cat" commands0

% cat adder4.v

% cat fixture.v

Setting u" t%e Simulation En*ironment

A set of commands must be entered to setup the simulation en!ironment. These

commands ha!e been entered into a file for each of the '(A tools a!ailable on thenet$or.

Use the follo$ing command to setup for Cadence *C tools0+ source !ee!setu"!cadence!ic,setu"cmd (n"u.)

/unning Logic Simulation

Use the follo$ing command to run Verilog-XL simulatin0

% verilog adder4.v fixture.v

The follo$ing output $ill be displayed after you enter the abo!e command0......

Compiling source file "adder4.v"

Compiling source file "fixture.v"Highest level modules:

fixture

0 a=xxxx b=xxxx ci=x co=x sum=xxxx 10 a=0000 b=0000 ci=0 co=0 sum=0000

20 a=0100 b=0010 ci=1 co=0 sum=0111

0 a=1000 b=1001 ci=0 co=1 sum=0001 40 a=0011 b=0010 ci=1 co=0 sum=0110

!0 a=0000 b=0101 ci=0 co=0 sum=0101

0 a=0011 b=0010 ci=1 co=0 sum=0110 #0 a=1001 b=1001 ci=1 co=1 sum=0011

$0 a=0011 b=0001 ci=1 co=0 sum=0101

0 simulation events %use &profile or &listcounts option to count'

C() time: 0.1 secs to compile & 0.0 secs to lin* & 0.0 secs in simulation

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+nd of ,+-/3/ 2.# an 2#5 2000 10:06:04

The simulation result is also stored in the file !erilog.log.

Vie#ing 0a*e1orms1ou may ha!e noticed the t$o lines in the fixture.! file0

2dum"1ile('adder3*cd)4

2dum"*ars(56"a6"76"ci6 o7s,s6 o7s,co)4

These t$o lines tell Verilog-XL to generate the necessary information to display$a!eforms. A file called adder6.!cd" is generated during the simulation. This file is anA)C** file contains all the !alue changes for the list of !ariables specified in the2dum"*ars()command. A Value C%ange Dum" (VCD)file can be used for manydifferent purposes including $a!eform generation and test !ector generation. any testrelated tools support VC( format.

The first argument in the Ddump!ars9: tas indicates the le!el of hierarchy to monitor$hen the arguments follo$ing it is a bloc name.

*f no argument is gi!en to Ddump!ars9:# all the !ariables in the design $ill be monitored.This is not recommended for large designs since the file siJe can be !ery large.

The signalscan $a!eform !ie$er can be used to !ie$ the simulation output. The product$as de!eloped by a company called (esign Acceleration *ncorporated in )an Kose. Thecompany $as purchased by Cadence in late F>>>.

)ignalscan uses a format called 'trn" type file to record data e!ent transactions.o$e!er# the tool can also con!ert the VC( file into a T/N file.

'Signalscan %as 7een renamed to 'sim*ision 78 Cadence in recent releases

To start the signalscan tool# type the follo$ing at the Unix%Linux prompt0

+ signalscan or sim*ision

The )ignal scan control $indo$ $ill sho$ up. Clic on the 9"enSim&ile" button or&ile:;9"en Sim &ile

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After the translation# the DA= Signalscan Design >ro#ser" $indo$ comes up. Clic onthe instance name 9not the module name: under the =nstances in Current Contet"panel. Note that you can mo!e up and do$n the design hierarchy by clicing on a moduleand the CDU"Sco"e" button on the button bar.

5nce the instance of interest is selected# all the !ariables in that instance $ill sho$ in theNodes!Varia7les in Current Contet" panel.

Clic on the !ariable%node name you $ant to !ie$# and they $ill sho$ up in the !ariablelist on the left hand side of the DA= Signalscan Design >ro#ser" $indo$. 1ou mayalso clic on the ?etAllVars" button to select all !ariables under the module.

After all the !ariables ha!e been selected# clic on the AddTo0a*e" button to bring upthe $a!eform $indo$. 5nce this $indo$ comes up# you can still go bac to the (esignro$ser $indo$ to select more signals to add to the $a!eform !i$er.

Use the 9"tions:;De1ine Pre1erences

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2ith the abo!e lines# a directory called debugger.$a!e" $ill be created after you runsimulation0

n"u.ren8l;"#d

!%ome!ren8l

n"u.ren8l;ls de7ugger#a*ede7uggerdsn de7uggertrn

n"u.ren8l;

)im!ision can open the file debugger.trn directly.

Bonitoring all Signals*f you $ant to monitor all the signals# you can lea!e out the !ariable list in the Ddumpfiletas0

Ddum"*ars9:;

The resulting VC( file $ill contain all the !ariables in the design. Note that doing this$ill cause your file to be significantly larger for a large design.

Using Verilog-XL 1rom ome1ou may use the Cadence Verilog-XL from home if you ha!e internet access. The firststep in setting up the home to N&U Unix connection is to do$nload the ssh" utility fromN&U *T ser!ices. &lease contact N&U *T on ho$ to setup ssh" for your home computer.

5nce you ha!e ssh" setup completed# you may use the putty.exe" utility to connect to aUnix machine. Among the many machines# npuFH.npu.edu" is one of the faster ones.

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