以 0.18 製程模擬二極差動延遲環型壓控振盪器 學生:張冠程...

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以 0.18 以以以以以以以以以以以以以以以以以 以以 以以以 以以以 以以以以 以以以 以以 1.以以以以 以以以以以以以以以以以以 以以以以 (PLL) 以 以以以以以以以以以以以以以 以以以以以以以以以以以以 以以以以以以以以以以以以以以 一,, 以以以以以 (VCO) 以以以以以以以以以以以以以以以以 ( 以以以以以以以以以以以以 以以以以以以以以以以以以 以以以以以以以以以以 、、 ) 以以以 以以以以以以以以 以以以以以以以以以以以以以以以以以以以以以以以 以以以以以以以以以以以以以以以以以以以以以以以以以以以以以以以 ,,。 以以以以以以以以以以以 以以以以以以 以以以以以以以以以以 以以以以以以以 以以以以以以以以以以以 以以以以以以以以以以以以以以以以以以 ,一、、、, 以以以以以 以以以以以以 一, LC 以以以以以以以以以以以LC 以以以以以以以以 Q 以以以以以以以以以以 以以以以以以以以以以 以以以以以以以 ,, 以以以以以以 以以以以以以 以以以以以以以以以以 ,體,。 以以以以以以以以以以以以以以以以 以以以以以以以以以以以以以以以 以以以以以 以以以以以以以 以以以以以以以以以以以以以以以以以以以以 、,一、。 以以 以以 以以以以以 以以以以以 2.63GHZ~0.94GHz 以以 2. 以以以以以以以以以 以以以以以以以以以以以以以以以以以 以以以以以以以以以以以以以以以以以以 以以以以以以以以以 以以 以以以以以以以以以以以以以以以以以以 ,一。一 S uper Buffer 以以以以以以以以以以以以以以以以以以 以以以以以 以 ,,一 Vctrl 以以以以以以以以 Super Buffer 以 以以 以以 VDD 以以以以以以以以以以以以以以以以以以 以以以以以以以以以 以以 ,,, Buffer 以以以以以以以以以以以以以以以以以以以以以以以以以 以 一。 I 以以以以以以以以以以以以以 以以以以以以 State1 以以 以以以以以 Stat e2 State2 以以以 State1 以以以以以以以以以以 ,。 以 I 以以以以以 以以以以以 5. 以以 以以以以以以以以以以以以以以以以以 以以以以以以以以以以以以以以以以以以以以以 以以 以以以以以以以以以以以以以以以以以以以以以以以 以以 ,。一。 以以以以以以以以以以以 以以以以以以 以以以以以以以以以以以以以以以以以 ,、 (VCO) 以以以 以以以以以以以以以以 以以以以以以 。, PMOS 以以以以以以以以 (gm) 以以 以以以以以以以以以以 以以以以以以以 體,。, VCO 以以以以以 (PLL) 以以以以以以以 以以以以以以以以以以 PL L VCO 以以以以以 以以以以以 11 以以以以以以以以以以以以以 IC 以以以以以以以以以以以以以以以以以以以以以以以以以以 以以以以 ,。 以以以以以以以以 以以以以以以以以以以以以以以以以以以以 ,。 以以 以以以以以 H-spice 以 ADS 以以以以以 以以以以以以以以以以以以以 以以以以以以以以以以以以以以以以以以 、,。 以以 以以以以以 以以 以以以以以 . 以以以以 以以以以以 H-spice 以 Advanced Design System 以以以以 以以以以以以以以以 以以 ,、 - 以以以以以 以以 - 以以 以以以 以以以以以以以以以以以以以以以以以 、。 以以 以以以以以以以以以以 以以 以以 Layout 以 以以 以以以以以以以以以 以以以以以 11.93MV~7.3mW 以以 4. 以以以以 以以 以 Bi-CMOS 以以以以以以以以以以以以以以以以以 以以以 以以 。一 Vctrl=1.8V VDD=1.8V 以以以以以以以以以以 以以以以 以以 以以以以 以以 以以以以 (Vctrl=0.9V VDD=1.8V) 以以以 以以以以 (Vctrl=1.8V VDD=1.8V) 以以以以以以以以以以以以以 0.247dBm 以以以以以以以 以以 以 以以以以 ,一,一 -5dBm 以以以以以以以以 以以以以以以以以以以以以 以以以以以以以以 以以 以以以以以以以 以以以以以以以以以以以以以以以以以 ,一, -120 dBc/Hz(@1MHz 以以 ) 以以以 以以以以以以 以以以以以以以以以 -124.5 dBc/Hz(@1MHz 以以 ) 以以以以以以以以以 ,。 GND VDD Buffer Super Buffer L C1 C2 GND 以以以以 Z Delay cell Delay cell Vo1+ Vo1- Vo2+ Vo2- VCTRL ` GND GND IN+ IN- VCTRL VDD OUT- OUT+ M b1 M p2 M p1 M p1 M p2 M n1 M n1 R L C1 C2 GND V out out Vo1+ Vo1- Vo2+ Vo2- State1 H L H L State2 L H L H 0.8 1 1.2 1.4 1.6 1.8 VCTRL 0.5 1 1.5 2 2.5 3 Frequency(G H z) FF TT SS FF TT SS 0.8 1 1.2 1.4 1.6 1.8 V ctrl 4 6 8 10 12 14 16 D issipation(m W ) FF TT SS FF TT SS 以以以以以以 以以以以以 99 以以以 以以以以以以以以以

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崑山科技大學 電子工程系 99 學年度 學生實務專題成果展. 以 0.18 製程模擬二極差動延遲環型壓控振盪器 學生:張冠程 李銘偉指導教授:蔡澈雄 老師. 研究目的 在現在的電子及通訊電路中,鎖相迴路 (PLL) 是一種常見且在無線通訊系統中,受到相當廣泛運用的電路,其中鎖相迴路裡的核心電路就是壓控振盪器 (VCO) ,然而壓控振盪器容易受到環境的影響 ( 如電源電壓變化時的穩定度、環境溫度變化時的穩定度、外界磁場與振動的影響 ) 以及電路本身的雜訊影響,使得振盪訊號在頻譜上發生偏移或是相位雜訊太大,而這些情形將會影響到鎖相迴路無法進行相位鎖定與輸出波形的跳動。 - PowerPoint PPT Presentation

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  • 0.18

    (PLL)(VCO)()LCLCQ2.63GHZ~0.94GHz 2.

    Super BufferVctrlSuper BufferVDDBuffer

    IState1State2State2State1

    I 5. (VCO)PMOS (gm)VCO (PLL)PLL VCO 11IC H-spiceADS .

    H-spiceAdvanced Design System--

    Layout 11.93MV~7.3mW 4.

    Bi-CMOS Vctrl=1.8VVDD=1.8V(Vctrl=0.9VVDD=1.8V) (Vctrl=1.8VVDD=1.8V)

    0.247dBm-5dBm-120 dBc/Hz(@1MHz)-124.5 dBc/Hz(@1MHz) 99

    Vo1+Vo1-Vo2+Vo2-State1HLHLState2LHLH

    1

    Z

    Delay cell

    Delay cell

    Vo1+

    Vo1-

    Vo2+

    Vo2-

    VCTRL

    `

    GND

    GND

    IN+

    IN-

    VCTRL

    VDD

    OUT-

    OUT+

    Mb1

    Mp2

    Mp1

    Mp1

    Mp2

    Mn1

    Mn1

    R

    L

    C1

    C2

    GND