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Low-Power Self Reconfigurable Multiplexer Based

Decoder for Adaptive Resolution Flash ADCs

Chetan Vudadha, Goutham Makkena, M Venkata Swamy Nayudu, Sai Phaneendra P, Syed Ershad Ahmed,Sreehari Veeramachaneni, N Moorthy Muthukrishnan, M.B. Srinivas

Department of Electrical Engineering,

Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, India.

{chetan, h2009002, h2009007, h2009009, syed, srihari, moorthy, mbs}@bits-hyderabad.ac.in

AbstractThis paper presents a new improved multiplexer

based decoder for flash analog-to-digital converters. The

proposed decoder is based on 2:1 multiplexers. It calculates the

binary code for low operand length thermometer code at initial

stages and groups the output of initial stages to generate the

final result. The proposed decoder can be configured to

operate on thermometer code with reduced length without anyextra overhead. This self-reconfigurable property is

particularly useful in adaptive resolution analog-to-digital

converters. Simulation results indicate that the proposed

decoder results in reduced delay, power and power delay

product when compared to existing digital decoders for flash

analog-digital converters.

Keywords-Flash converter; Multi-precision;

Reconfigurable;Low power; Thermometer-to-binary ;

I. INTRODUCTIONAnalog to-digital converter (ADC) is a key functional

block in the design of mixed signal, system on chip andsignal processing applications. Many types of ADCs have

been developed for different applications [1]. High speedADCs are often based on flash structure [2-4] shown inFigure 1. Recently flash ADCs with adaptive resolution havealso been proposed [5-6]. In the flash ADC implementationthe input signal is applied to inputs of 2

N-1 comparators,

where N indicates the resolution of the ADC. Eachcomparator is connected to a reference voltage commonlygenerated by a resistive ladder. The output of comparator ishigh if the input voltage is larger than the reference voltageat the input of comparator otherwise the output is low. Hencethe output pattern corresponds to thermometer code. Thethermometer code is converted in to binary code by (2

N-1)-

to-N decoder generally called as Thermometer-to-Binarydecoder. Many implementations have been proposed for

thermometer to binary conversion [7-13]. A comparison ofdifferent decoders was presented in [7]. Folding techniquesfor the decoders have been presented in [13] [15]. Thesetechniques result in reduced hardware complexity.

For low resolution and low speed ADCs, the inputs to thedecoder will be perfect thermometer code. As the resolutionand speed of operation of the ADC increase, bubble errorsare introduced in the thermometer code. The bubble errorsare unwanted digital zeros introduced in the thermometercode and are result of many sources, for example: clock

jitter, device mismatch, meta-stability and error probabilityof the comparators etc.

This paper presents an improved Multiplexer (MUX)based decoder for flash ADCs. The proposed decoder can beconfigured to operate on thermometer code with reduced

operand length without any extra overhead and is suitable foradaptive resolution ADC designs. The decoder can also beconfigured to operate on multiple thermometer codes ofreduced length. The proposed decoder results in reduceddelay and power than the existing digital decoders.

Figure 1. Illustration of Flash ADC

The rest of the paper is organized as follows: Section IIdescribes the related work. Section III describes the proposedimproved MUX based decoder. This section also explainsthe self reconfigurable property of the proposed decoder.Simulation results are presented in section IV andconclusions are drawn in section V.

II. RELATED WORKA common approach to decode the thermometer code is

to use a gray or binary ROM based decoder [8-9]. The basicstructure of the ROM based decoder is shown in Figure 2.The ROM based approach has 2 stages. In the first stage thethermometer code is converted in to 1-out of-2N-1 code. Thiscan be done by using array of NAND gates as shown in theFigure 2. The second stage is the ROM structure which takesthe 1-out-of 2

N-1 code as input and selects appropriate row in

the ROM. Although ROM decoder approach is simple andstraight forward to design, it is however slow and consumeslarge power due to a constant static current used to preset theROM encoder [9]. Another problem of binary ROM decoder

2012 25th International Conference on VLSI Design

1063-9667/12 $26.00 2012 IEEE

DOI 10.1109/VLSID.2012.84

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is the bubble error. When bubble error occurs there are morethan one 1s in 1-out of-2N-1 code. Hence more than onerow in the ROM will be enabled resulting in erroneousbinary code.

Many digital decoders for converting thermometer codeto binary code have been presented in the literature. Thestraight forward approach is the Wallace tree based decoder[10] [7], which count the number of number of 1s. Thisapproach has the benefit of bubble suppression. Anotheradvantage of using ones counter as a decoder is thatdepending on the speed of ADC a suitable ones countertopology may be used by a speed power trade off. Thedisadvantage of this approach is that it results in large delayand power.

Figure 2. Flash ADC implmentation with ROM Decoder

A more power and delay efficient approach of convertingthermometer to binary code is to use Fat tree based decoder[11]. Fat tree structure has two stages. The first stageconverts the thermometer code to 1-out of-2N-1 code. Thesecond stage converts the 1-out of-2N-1 code to binary codeusing multiple trees of OR gates. This results in reduced areaand delay when compared to Wallace tree based decoder.Figure 3 shows the implementation of fat tree based decoderfor 15-bit thermometer code input.

Figure 3. Fat Tree Based Decoder [11]

A more optimized implementation of the fat tree basedencoder is presented in [12]. This approach reduces the arrayof OR gates into NAND-NOR pairs. The NAND-NOR gateswere implemented using a pseudo-dynamic CMOS logic.

A MUX based thermometer to binary decoder isproposed in [13]. This decoder results in short critical pathand small area. At each level, the input thermometer code isdivided in two and one of the bits in the binary output iscalculated. Figure 4 shows the implementation of MUXbased decoder for 15-bit thermometer code input. Thedisadvantage of this approach is that it results in huge fan-outin the critical path. The MUX based implementation of 15-bit thermometer code to binary decoder results in fan-out of7 in level 1 and 4 in level 2. The increased fan-out results inincreased power consumption and delay.

Figure 4. Existing MUX Based Decoder [13]

III. PROPOSED IMPROVED MUX-BASED DECODERA.

Basic IdeaThe main idea behind the design of the proposed MUX

based decoder is to group the results of smaller length MUX-based decoders to form a larger decoder for thermometer tobinary conversion. This idea is explained by designing a 7-bit thermometer code to binary decoder using a 3-bitthermometer to binary code decoder.

A simple circuit to convert 3-bit thermometer code tobinary code along with the truth table for the same is shownin the Figure 5. Here T3-T1 represents the inputThermometer code and B2-B1 represents the binary code.

Figure 5. 3-bit Thermometer to binary decoder for 2-bit Flash ADC

Now the 3-bit thermometer to binary decoder can be usedto design a 7-bit thermometer to binary decoder. The truth

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table and pictorial representation of the design of 7-bitthermometer to binary decoder using the 3-bit thermometerto binary decoder is shown in Figure 6. In the truth table, T7-T1 represents the input thermometer code and B3-B1represents the binary code.

As seen from truth table

B3= T4, and

When T4 = 0 the B2-B1 are equivalent to the outputs of 3-bit thermometer to binary decoder with T3T2T1 as inputs.

When T4 = 1 the B2-B1 are equivalent to the outputs of 3-bit thermometer to binary decoder with T7T6T5 as inputs.

Figure 6. Truth table for 7-bit thermometer to binary decoder

Hence using a T4 as selection signal, 7-bit thermometer tobinary decoder can be constructed using 3-bit thermometer tobinary decoders and array of MUXs. Such animplementation of 7-bit Thermometer to binary decoder isshown in the figure 7, the dotted block indicates 3-bitthermometer to binary decoder.

Figure 7. Proposed 7-bit Thermometer to binary decoder for 3-bit Flash

ADC

The 7-bit thermometer to binary converter uses two 3-bit

thermometer to binary converters. Two MUXs are used forimplementing the selection. The outputs of 3-bit decoders arefed to these MUXs and the selection signal T4 selects outputsfrom either one of the dotted 3-bit decoders.

Consider example where the 7-bit thermometer code T7-T1 is given by 0111111, since the T4 signal being 1indicates that all the bits to right hand side of T4 i.e. T3-T1 are1 making the binary code B3-B1 greater than 100. TheLSB bits B2-B1 are now defined by the number of 1s

present in the left hand side of T4 signal, which is equal totwo i.e. 10. This now represents the LSB bits B2-B1 of thefinal binary code.

This design methodology can be extended to implement a2N-1 bit decoder that can be used for an N-bit flash ADC. Ageneralized implementation of a 2N-1 bit decoder is shown inthe figure 8.

Figure 8. Generalized Implmentation of 2N-1 thermometer to binarydecoder for N-bit Flash ADC

A 2N

-1 bit decoder can be designed by using two 2N -1

-1bit decoders and an array of MUXs to generate the binary

code BN-B1 from the thermometer code T (2N

-1) - T1. Eachof the 2N -1-1 bit decoders can further be designed using two2

N -2-1 bit decoders and an array of MUXs. This iterative

implementation can be done until the basic element, i.e. a 3-bit thermometer to binary decoder, is reached. Thisimplementation results in a more regular structure.

The proposed 15-bit thermometer to binary decoder isshown in figure 9(d).This decoder results in a more regularstructure, same number of gates and less maximum fan-outthan the existing MUX based decoder [13]. The proposeddecoder results in reduced number of gates when comparedto Wallace tree decoder and fat tree decoders.

B. Critical pathdelay comparisionThe critical path delay for existing and proposed

decoders is shown in figure 9. The proposed MUX baseddecoder has three gates delay in its critical path for a 15-bitthermometer to binary decoder shown in figure 9(d).Although the existing 15-bit thermometer to binary MUXbased decoder has a 3 gate delay in the critical path, amaximum fan-out of 7 for the input signal at the first stageresults in increased delay. The proposed decoder has amaximum fan-out on input signal in the last stage of thecircuit and hence does not occur in the critical path.

The 15-bit Wallace tree based decoder and Fat tree baseddecoder has a critical path delay of 7 gates and 4 gatesrespectively. The critical path delay in terms of gates fordifferent 63-bit decoders, which can be used in 6-bit flashADC are presented in Table I.

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(a) (b) (c) (d)

Figure 9. Different 15-bit Thermometer to Binary Decoders (a) Wallace Tree Based (b) Fat-tree Based (c) Existing MUX Based (d) Proposed

TABLE I. CRITICAL PATH DELAY COMPARISON FORDIFFERENTDECODERS

63-bit Decoder

(for 6-bit Flash

ADC)

No. of gates in Critical

Path Delay

Maximum fan-out

in the Critical path

Wallace Tree 18 2

Fat Tree Decoder 6 2

Existing MUX-based 5 31

Proposed MUX-based 5 2

C. Self-Reconfigurable PropertyThe proposed thermometer to binary decoder is designed

by grouping the signals generated from the smallerthermometer to binary converters. Hence the proposeddecoder has a unique self reconfigurable property.

Consider a 15-bit thermometer to binary decoders shownin the Figure 9(d). These decoders can be configured tooperate as a 7-bit thermometer to binary decoders by makingthe MSB bits T8-T15 as logic zero. Since the MSB bits aretied to logic zero the gates to which these signals are fed donot have switching activity. The gates with switching activityfor the existing and proposed decoders are shown in grey inthe Figure 9. The Table II shows the number of gates withswitching activity for different decoders, when 15-bitdecoders are used to operate on Thermometer codes of 7-biti.e. when 4-bit flash ADC is used for 3-bit resolution.

TABLE II. GATES WITH SWITCHING ACTIVITY FOR LOWERRESOLUTION OPERATION

15-bit decoders used

as 7-bit decoder by

zero padding

(Figure 6)

Decoder No. gates with

switching activity

Wallace Tree 21

Fat Tree Decoder 18

Existing MUX-based 11

Proposed MUX-based 7

As seen from the Table II the gates with switchingactivity are less in the proposed decoder when compared to

the existing decoder designs. The switching activity isdirectly related to dynamic power, which forms a majorcomponent of the total power consumption. Hence theproposed decoder results in low power consumption whenoperated for thermometer codes with smaller length and isideally suited for adaptive resolution ADCs.

Further the proposed decoder can be configured tooperate on multiple thermometer codes. The 15- bitthermometer to binary decoder can be operated as two 7-bitthermometer to binary decoders by making the T8 signal aslogic zero and latching the intermediate outputs of the 7-bitthermometer to binary decoder which has T9-T15 as inputs.This can also be achieved by making the T8 signal as logicone and latching the intermediate outputs of the 7-bitthermometer to binary decoder which has T1-T7 as inputs.This property is unique to the proposed MUX based decoderand is not present in any of the existing decoder designs.

Since the proposed decoder can be configured to operateon single or multiple thermometer codes of shorter lengthwithout any extra circuitry, it is said to be self-reconfigurable.

D.Bubble Error CorrectionWallace tree based decoder has inherent bubble

suppression property, where as for other decoders, includingthe proposed decoder, need a bubble correction circuit forcorrecting the bubble errors. The different bubble correction

circuits that can be used for different decoders are presentedin [14]. Since the basic operation of the proposed MUXbased decoder is similar to the existing MUX based decoder,the same bubble correction circuit that was used for MUXbased decoder in [14] can be used for the proposed improvedMUX based decoder. Figure 10 shows the bubble errorcorrection circuits for single bubble and double bubble errorrespectively. In the Figure 10 T1-T8 signals representsthermometer code with bubble errors.

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Figure 10. Circuit for (a) Single Bubble Error Correction. (b) DoubleBubble Error Correction.

E.Heterogenous DecodersIn the proposed methodology of designing thermometer

to binary decoders for flash ADC, smaller decoders wereused to implement larger decoders as shown in the Figure 8.Any of the existing decoders like Wallace tree decoder or Fattree decoder can be used for implementing the smaller

decoders. This results in a family of heterogeneous decoders.

Consider as an example a 7-bit decoder shown in Figure5. The dotted block in the Figure 5 indicates a 3-bit MUXbased decoder. This 3-bit decoder can be a fat tree baseddecoder of a Wallace tree based decoder.

One such implementation which uses a combination of 3-bit counter and proposed methodology is shown in the Figure11. Since the selection signal used for MUXs is critical theycan be made bubble tolerant. The remaining signals are usedas inputs to a 3-bit counter.

Figure 11. Heterogeneous Decoder

IV. SIMULATION RESULTS AND COMPARISIONSAll the architectures were structurally described using

Verilog HDL and simulated using Cadence Incisive UnifiedSimulator (IUS) v6.1 covering all functional combinations.

The designs were mapped on the TSMC 180nm Technologywith slow_normal library (operating conditions 1.8 V, 25C),and slow_highVt(operating conditions 0.9 V, 125

oC) using

Cadence RTL Compiler v7.1.The power analysis is done onall designs with 50% toggle rate at 500MHz frequency.

Table III and IV show simulation results for all thearchitectures for 63-bit thermometer to binary decoders i.e.,for a 6-bit resolution, for slow_normal and slow_highvtlibraries respectively.

TABLE III. SIMULATION RESULTS FOR63-BIT (FOR6-BIT FLASH ADC)THERMOMETER TO BINARY DECODERS FOR SLOW_NORMAL LIBRARY

Delay

(nS)

Area

(m2)

Power

(W)

Power-Delay

Product

(fJ)

Wallace Tree 1.926 1276.430 351.428 676.850

Fat Tree 0.701 752.170 62.412 43.751

Existing MUX

Based

1.021 361.973 44.745 45.685

Proposed 0.546 361.973 44.732 24.424

TABLE IV. SIMULATION RESULTS FOR63-BIT (6-BIT RESOLUTION)THERMOMETER TO BINARY DECODERS FOR SLOW_HIGHVT LIBRARY

Delay

(nS)

Area

(m2)

Power

(W)

Power-Delay

Product

(fJ)

Wallace Tree 2.582 1276.430 340.879 880.15

Fat Tree 0.931 752.170 60.054 55.910

Existing MUX

Based

1.334 361.973 42.953 57.299

Proposed 0.752 361.973 42.565 32.009

Wallace tree decoder has more power, area and delaycompared to the other architectures. Delay of the fat treebased decoder falls in between the proposed architecture andthe existing MUX based decoder. Because of its inherent treestructure, the area occupied by the fat tree based decoder ismore compared to existing MUX based and proposeddecoder.

The design presented in [12] optimizes the fat tree baseddecoder at transistor level using pseudo dynamic CMOSlogic. In this paper, we have concentrated on gate levelimplementation of the design and hence comparison of [12]with the proposed decoder has not been done.

Although the proposed and existing MUX baseddecoders have same area, the proposed decoder results inlower delay, as it removes high fan-out in the critical pathwhich the existing MUX based decoder suffers from.

The proposed architecture has the same number of gatesas the existing MUX based design and hence the powerdissipated by both the decoders is almost the same.

A.Power Results for re-configurabilityThe table V and VI show the power consumption of all

the decoders of 63-bit length (for 6-bit flash ADC), whenoperated for lesser bit lengths i.e., for different resolutions,for slow_normal and slow_highvt libraries respectively.

The existing MUX based decoder has no self-reconfigurable property. This results in higher power

consumption for lower resolution inputs when compared tofat tree and proposed decoders. The power consumption ofthe existing MUX based decoder for lower resolution islower than its higher resolution counterpart because theactivity is less in lower resolution inputs.

Wallace tree, fat tree and proposed decoders have self-reconfigurable property as discussed in section III. But thenumber of gates the Wallace tree and fat tree based decoders

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require is high, when compared to the proposed decoder andhence consume more power.

TABLE V. POWERCONSUMPTION FOR DIFFERENT OPERAND LENGTHSIN SLOW_NORMAL CORNER LIBRARY.ALL UNITS ARE IN W

7-bit

(for 3-bit

flash ADC)

15-bit

(for 4-bit

flash ADC)

31-bit

(for 5-bit

flash ADC)Wallace Tree 56.516 104.859 184.889

Fat Tree 9.737 17.048 31.812

Existing

MUX Based 11.523 19.995 32.202

Proposed 8.413 13.571 23.538

TABLE VI. POWERCONSUMPTION FOR DIFFERENT OPERAND LENGTHSIN SLOW_HIGHVT CORNER LIBRARY.ALL UNITS ARE IN W

7-bit

(for 3-bit

flash ADC)

15-bit

(for 4-bit

flash ADC)

31-bit

(for 5-bit

flash ADC)

Wallace Tree 50.702 98.317 177.047

Fat Tree 7.229 14.558 29.367

Existing

MUX Based 10.055 18.363 30.107

Proposed 7.013 12.116 21.979

B.Bubble Error Correction ResultsThe tables VII and VIII show the results of the proposed

decoder with single and double error bubble correctioncircuits shown in Figure 7.

TABLE VII. SIMULATION RESULTS FORPROPOSED DECODER WITHSINGLE AND DOUBLE BUBBLE ERRORCORRECTION IN SLOW_NORMAL

LIBRARY

Bubble Error

Correction

Delay

(nS)

Area

(m2)

Power

(W)

Power-Delay Product

(fJ)

Single 0.698 580.709 63.028 43.994

Double 0.739 624.456 52.278 38.633

TABLE VIII. SIMULATION RESULTS FORPROPOSED DECODER WITHSINGLE AND DOUBLE BUBBLE ERRORCORRECTION IN SLOW_HIGHVT

LIBRARY

Bubble Error

Correction

Delay

(nS)

Area

(m2)

Power

(W)

Power-Delay Product

(fJ)

Single 0.950 580.709 54.672 51.9384

Double 1.006 624.456 49.443 49.740

The proposed decoder with single bubble correctioncircuit has 21.7%, 37.9% and 29% delay, area and poweroverheads respectively under slow_normal libraryconditions.

The proposed decoder with double bubble correctioncircuit has 26.1%, 42.15% and 14.4%delay, area and power

overheads respectively under slow_normal libraryconditions.

V. CONCLUSIONA new improved multiplexer based decoder for flash

analog-to-digital converters is proposed, which convertsthermometer code to binary code. The proposed decoder isdesigned by grouping the signals generated from the smaller

thermometer to binary decoders. It can be configured tooperate on thermometer code with reduced length withoutany extra overhead which is suitable for adaptive resolutionanalog to digital converters. Simulation results indicate thatthe proposed decoder results in better performance whencompared to the existing decoders in terms of power, delayand area.

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