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aADMC200

FUNCTIONAL BLOCK DIAGRAM

RESETWR

A03RDCS

IRQ

CLK

REFOUT

REFINCONVST

UVW

AUXPWMSYNC

AAP

BBP

CCP

STOP

EMBEDDEDCONTROL

SEQUENCER

INTERNALREFERENCE

11-BITA/D

CONVERTER

12-BITPWM TIMER

BLOCK

CONTROLREGISTERS

VECTORTRANSFORMATION

BLOCK

DATABUS

CONTROL BUS

D0 D11

Motion Coprocesso

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

FEATURES

Analog Input Block11-Bit Resolution Analog-to-Digital (A/D) Converter4 Single-Ended Simultaneously Sampled Analog Inputs3.2 s Conversion Time/Channel0 V5 V Analog Input RangeInternal 2.5 V ReferencePWM Synchronized Sampling Capability

12-Bit PWM Timer BlockThree-Phase Center-Based PWM1.5 kHz25 kHz PWM Switching Frequency RangeProgrammable DeadtimeProgrammable Pulse DeletionPWM Synchronized OutputExternal PWM Shutdown

Vector Transformation Block12-Bit Vector TransformationsForward and Reverse Clarke TransformationsForward and Reverse Park Rotations2.9 s Transformation Time

DSP & Microcontroller Interface12 Bit Memory Mapped RegistersTwos Complement Data Format

6.25 MHz to 25 MHz Operating Clock Range68-Pin PLCC PackageSingle 5 V DC Power SupplyIndustrial Temperature Range

GENERAL DESCRIPTIONThe ADMC200 is a motion coprocessor that can be used witheither microcontrollers or digital signal processors (DSP). Itprovides the functionality that is required to implement a digitalcontrol system. In a typical application, the DSP or micro-controller performs the control algorithms (position, speed,torque and flux loops) and the ADMC200 provides the neces-sary motor control functions: analog current data acquisition,vector transformation, and PWM drive signals.

PRODUCT HIGHLIGHTSSimultaneous Sampling of Four InputsA four channel sample and hold amplifier allows three-phasemotor currents to be sampled simultaneously, reducing errors

from phase coherency. Sample and hold acquisition time is1.6 s and conversion time per channel is 3.2 s (using a 12.5 MHzsystem clock).

Analog Devices, Inc., 1995

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 617/329-4700 Fax: 617/326-8703

Flexible Analog Channel SequencingThe ADMC200 supports acquisition of 2, 3, or 4 channels pergroup. Converted channel results are stored in registers and thedata can be read in any order. The sampling and conversiontime for two channels is 8 s, three channels is 11.2 s, and four

channels is 14.4 s (using a 12.5 MHz system clock).Embedded Control SequencerThe embedded control sequencer off-loads the DSP or micro-processor, reducing the instructions required to read analog in-put channels, control PWM timers and perform vector trans-formations. This frees the host processor for performing controlalgorithms.

Fast DSP/Microprocessor InterfaceThe high speed digital interface allows direct connection to16-bit digital signal processors and microprocessors. TheADMC200 has 12 bit memory mapped registers with twoscomplement data format and can be mapped directly into thedata memory map of a DSP. This allows for a single instruction

read and write interface.IntegrationThe ADMC200 integrates a four channel simultaneous sam-pling analog-to-digital converter, analog reference, vector trans-formation, and three-phase PWM timers into a 68-pin PLCC.Integration reduces cost, board space, power consumption, anddesign and test time.

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ADMC200SPECIFICATIONS(VDD = +5 V 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock =12.5 MHz; TA = 40 C to +85 C unless otherwise noted)Parameter ADMC200AP Units Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER 1

Resolution 11 Bits Twos Complement Data FormatRelative Accuracy 2 LSB max Integral NonlinearityDifferential Nonlinearity 2 LSB max No Missing Codes GuaranteedBias Offset Error 5 LSB max Any ChannelBias Offset Match 4 LSB max Between ChannelsFull-Scale Error 5 LSB max Any ChannelFull-Scale Error Match 4 LSB max Between ChannelsConversion Time/Channel 40 System CLK CyclesSignal-to-Noise Ratio (SNR) 2 60 dB min f IN = 600 Hz Sine Wave, f SAMPLE = 55 kHz, 600 HzChannel-to-Channel Isolation Sine Wave Applied to Unselected Channels

Two-/Three-Phase Mode 60 dB maxThree-/Three-Phase Mode 55 dB max

ANALOG INPUTSInput Voltage Level 05 VoltsAnalog Input Current 100 A maxInput Capacitance 10 pF typ

TRACK AND HOLDAperture Delay 200 ns max Any ChannelAperture Time Delay Match 20 ns max Between ChannelsSHA Acquisition Time 20 System CLK Cycles

Droop Rate 5 mV/ms maxREFERENCE INPUT

Voltage Level 2.5 V dcReference Input Current 50 A max

REFERENCE OUTPUTVoltage Level 2.5 VoltsVoltage Level Tolerance 5 % max Full LoadDrive Capability 200 A max

LOGICVIL 0.8 V maxVIH 2.0 V minVOL 0.4 V max I SINK = 400 A, V DD = 5 VVOH 4.5 V min I SOURCE = 20 A, V DD = 5 VInput Leakage Current 1 A max

Three-State Leakage Current 1 A maxInput Capacitance 20 pF typ

12-BIT PWM TIMERSResolution 12 BitsProgrammable Deadtime Range 010.08 sProgrammable Deadtime Increments 2 System CLK Cycles 160 nsProgrammable Pulse Deletion Range 010.16 sProgrammable Deletion Increments 1 System CLK Cycle 80 nsMinimum PWM Frequency 1.5 kHz Resolution Varies with PWM Switching Frequency

(10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits, 5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre-quencies are Available with Lower Resolution

VECTOR TRANSFORMATION Park & Clarke TransformationRadius Error 0.7 % max

Angular Error 30 arc min maxReverse Transformation Time 37 System CLK CyclesForward Transformation Time 40 System CLK Cycles

EXTERNAL CLOCK INPUTRange 6.2525 MHz If > 12.5 MHz, Then It Is Necessary to Divide Down

via SYSCTRL Register

INTERNAL SYSTEM CLOCK Range 6.2512.5 MHz

POWER SUPPLY CURRENTIDD 20 mA max

NOTES1Measurements made with external reference.2Tested with PWM Switching Frequency of 25 kHz.

Specifications subject to change without notice.

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Table I. ADMC200 Timing Specifications (V DD = 5 V 5%; T A = 4 0 C to +85 C)

Number Symbol ADMC200 Timing Requirements Min Max Units

1 t perclk CLK Period 40 160 ns2 t pwh clk CLK Pulse Width, High 20 ns

3 t pwlclk CLK Pulse Width, Low 20 ns4 t sucsb_wrb CS Low before Falling Edge of WR 0 ns5 t suaddr_wrb ADDR Valid before Falling Edge of WR 0 ns6 t sudata_wrb DATA Valid before Rising Edge of WR 13 ns7 t hdwrb_data DATA Hold after Rising Edge of WR 4.5 ns8 t hdwrb_addr ADDR Hold after Rising Edge of WR 4.5 ns9 t hdwrb_csb CS Hold after Rising Edge of WR 4.5 ns10 t pwlwrb 1 WR Pulse Width, Low 20 ns11 t pwh wrb 1 WR Pulse Width, High 20 ns12 t hdwrb_clk_h 1 WR Low after Rising Edge of CLK 7 ns13 t suwrb_clk_h 1 WR High before Rising Edge of CLK 7 ns14 t suwrb_clk_l 1 WR High before Falling Edge of CLK 10 ns15 t hdclk_wrb_l 1 WR High after Falling Edge of CLK 10 ns16 t sucsb_rdb CS Low before Falling Edge of RD 0 ns17 t suaddr_rdb ADDR Valid before Falling Edge of RD 0 ns18 t hdrdb_addr ADDR Hold after Rising Edge of RD 0 ns19 t hdrdb_csb CS Hold after Rising Edge of RD 0 ns20 t pwlrdb RD Pulse Width, Low 20 ns21 t pwhrdb RD Pulse Width, High 20 ns22 t surdb_clk_h RD Low before Rising Edge of CLK 7.5 ns23 t hdrdb_clk_h RD Low after Rising Edge of CLK 7.5 ns24 t pwlresetb RESET Pulse Width, Low 2 tperclk ns

NOTE1All WRITES to the ADMC200 must occur within 1 system clock cycle (0 wait states).

Number Symbol ADMC200 Switching Characteristics Min Max Units

25 t dlyrdb_data DATA Valid after Falling Edge of RD 23 ns26 t hdrdb_data DATA Hold after Rising Edge of RD 0 ns

11

4

56

7

10

12 15 13

9

8

14

CLK

CS

A0A3

WR

DATA

NOTE:ALL WRITES TO THE ADMC200 MUST OCCUR WITHINONE SYSTEM CLOCK CYCLE (i.e. 0 WAIT STATES)

Figure 3. Write Cycle Timing Diagram

1

2 3

CLK

Figure 1. Clock Input Timing

24

CLK

RESET

Figure 2. Reset Input Timing

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ORDERING GUIDE

Part Temperature Package PackageNumber Range Description Option

ADMC200AP 40 C to +85 C 68-Pin PLCC P-68A

23

25

26

16

CLK

CS

A0A3

RD

DATA

22

20 21

18 19

17

Figure 4. Read Cycle Timing Diagram

ABSOLUTE MAXIMUM RATINGS*Supply Voltage (V DD ) . . . . . . . . . . . . . . . . . . 0.3 V to +7.0 VDigital Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

DDAnalog Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V DDAnalog Reference Input Voltage . . . . . . . . . . . . 0.3 V to V DDDigital Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V DDAnalog Reference Output Swing . . . . . . . . . . . . 0.3 V to V DDOperating Temperature . . . . . . . . . . . . . . . . . 40 C to +85 CLead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +280 C

*Stresses greater than those listed above may cause permanent damage to thedevice. These are stress ratings only, and functional operation of the device at theseor any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditionsfor extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the ADMC200 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

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registers respectively. The twos complement data is left justifiedand the LSB is set to zero. The relationship between input volt-age and output coding is shown in Figure 5.

0 1 1 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0

OUTPUTCODE FULL-SCALETRANSITION

0V 2.5 5V1LSB

INPUT VOLTAGE

FS = 5V

LSB =5V

2048

Figure 5. Transfer Function

Sample and HoldAfter powering up the ADMC200, bring the RESET pin low fora minimum of two clock cycles in order to enable A/D conver-sions. Before initiating the first conversion (CONVST) after a

reset, the SHA time of 20 system clock cycles must occur. Aconversion is initiated by bringing CONVST high for a mini-mum of one system clock cycle. The SHA goes into hold modeat the falling edge of clock.

Following completion of the A/D conversion process, a mini-mum of 20 system clock cycles are required before initiating an-other conversion in order to allow the sample and hold circuitryto reacquire the input signals.

If a CONVST is initiated before the 20 clock cycles haveelapsed, the embedded control sequencer will delay conversionuntil this requirement is met.

PWM TIMER BLOCK OVERVIEW

The PWM timers have 12-bit resolution and support program-mable pulse deletion and deadtime. The ADMC200 generatesthree center-based signals A, B, and C based upon user-suppliedduty cycles values. The three signals are then complementedand adjusted for programmable deadtime to produce the sixoutputs. The ADMC200 PWM master switching frequency canrange from 2.5 kHz to 20 kHz, when using a 10 MHz systemclock. The master frequency selection is set as a fraction of thePWMTM register. If the system clock is 10 MHz, then theminimum edge resolution available is 100 ns.

The output format of the PWM block is active LO. There is anexternal input to the PWM timers (STOP) that will disable allsix outputs within one system clock when the input is HIGH.

The ADMC200 has a PWM Synchronization output(PWMSYNC) which brings out the master switching frequencyfrom the PWM timers. The width of the PWMSYNC pulse isequal to one system clock cycle. For example, if the system clockis 10 MHz, the PWMSYNC width would be equal to 100 ns.

PWM Master Switching Period SelectionThe switching time is set by the PWMTM register which shouldbe loaded with a value equal to the system clock frequencydivided by the desired master switching frequency. For ex-ample, if the desired switching frequency is 8 kHz and the sys-tem clock frequency is 10 MHz, then the PWMTM registershould be loaded with 1250 (10 MHz/8 kHz). The PWMCHA,PWMCHB, and PWMCHC registers are loaded with the

ANALOG INPUT BLOCK The ADMC200 contains an 11-bit resolution, successiveapproximation analog-to-digital (A/D) converter with twoscomplement output data format. The analog input range is 2.5V (0 V5 V) with a 2.5 V offset as defined by REFIN. The on-chip 2.5 V 5% reference is utilized by connecting theREFOUT pin to the REFIN pin.

The A/D conversion time is determined by the system clock fre-quency, which can range from 6.25 MHz to 12.5 MHz. TheSample and Hold (SHA) acquisition time is 20 system clockcycles and is independent of the number of channels sampledand/or digitized. The input stage to the A/D converter is a fourchannel SHA which allows the four channels to be held simulta-neously and then sequentially digitized. Forty system clockcycles are required to complete each A/D conversion. The ana-log channel sampling is flexible and is programmable throughthe SYSCTRL register. The minimum number of channels perconversion is two. The throughput time of the analog acquisi-tion block can be calculated as follows:

t AA = t SHA + ( n t CONV )

wheretAA = analog acquisition time,n = # channels,tSHA = SHA acquisition time (20 system clock period),tCONV = conversion time (40 system clock period) per channel.

A/D Conversions are initiated via the CONVST pin. A syn-chronizing pulse (PWMSYNC) is provided at the beginning of each PWM cycle. This pulse can be used to synchronize theA/D conversion process to the PWM switching frequency.

Operating the A/D ConverterThe A/D converter can be set up to convert a sequence of chan-nels as defined in the SYSCTRL register (see Table V). Alwayswrite 0 to both Bits 0 and 1 of the SYSCTRL register. The de-fault channel select mode after RESET is to convert channels Vand W only. This is two-/three-phase mode. Three-/three-phasemode converts channels U, V, W and/or AUX. Three-/three-phase mode is achieved by writing a 1 to Bit 3 of the SYSCTRL register. After the conversion process is complete, the channelscan be read in any order.

There are two methods that can be used to indicate when theA/D conversions are completed and the data is ready: interruptdriven and software timing.

Interrupt Driven MethodInterrupts can be used to indicate the end of conversion for agroup of channels. Before beginning any A/D conversions, Bit 7of the SYSCTRL register must be set to 1 to enable A/D con-

version interrupts. Then, when an A/D conversion is complete,an interrupt will be generated. After an interrupt is detectedBit 0 of the SYSSTAT register must be checked to determine if the A/D converter was the source. Reading the SYSSTAT reg-ister automatically clears the interrupt flag bits.

Software Timing MethodAn alternative method is to use the DSP or microcontroller tokeep track of the amount of time elapsed between CONVSTand the expected completion time (n tCONV ).

Reading ResultsThe 11-bit A/D conversion results for channels U, V, W andAUX are stored in the ADCU, ADCV, ADCW and ADCAUX

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desired on-time and their values would be calculated as a ratioof the PWMTM register value. Note: Desired Pulse Density =(PWMCHx register)/( PWMTM register).

The beginning of each PWM cycle is marked by the PWMSYNCsignal. New values of PWMCHA, PWMCHB and PWMCHCmust all be loaded into their respective registers at least four sys-

tem clock cycles before the beginning of a new PWM cycle. Allthree registers must be updated for any of them to take effect.New PWM on/off times are calculated during these four clockcycles and therefore the PWMCHA, PWMCHB and PWMCHCregisters must be loaded before this time. If this timing require-ment is not met, then the PWM outputs may be invalid duringthe next PWM cycle.

PWM ExampleThe following example uses a system clock speed of 10 MHz.The desired PWM master switching frequency is 8 kHz and thedesired on-time for the timers A, B and C are 25%, 50% and10% respectively. The values for the PWMCHA, PWMCHB,and PWMCHC registers must be calculated as ratios of thePWMTM register (1250 in this example). To achieve theseduty cycles, load the PWMCHA register with 313 (1250 0.25), PWMCHB with 625 (1250 0.5) and PWMCHC with125 (1250 0.1).

Programmable DeadtimeWith perfectly complemented PWM drive signals and nonidealswitching characteristics of the power devices, both transistorsin a particular leg might be switched on at the same time, result-ing in either a power supply trip, inverter trip or device destruc-tion. In order to prevent this, a delay must be introducedbetween the complemented signal edges. For example, the ris-ing edge of AP occurs before the falling edge of A, and the fall-ing edge of the complemented A occurs after the rising edge of A. This capability is known as programmable deadtime.

The ADMC200 programmable deadtime value is loaded intothe 7-bit PWMDT register, in which the LSB is set to zero in-ternally, which means the deadtime value is always divisible bytwo. With a 10 MHz system clock, the 0126 range of values inPWMDT yield a range of deadtime values from 0 s to 12.6 sin 200 ns steps. Figure 6 shows PWM timer A with a program-mable deadtime of PWMDT.

PWMCHA - PWMDT

A

PWMTM

APPWMCHA + PWMDT

Figure 6. Programmable Deadtime Example

Pulse DeletionThe pulse deletion feature prevents a pulse from being gener-ated when the user-specified duty cycle results in a pulse dura-tion shorter than the user-specified deletion value. The pulsedeletion value is loaded into the 7-bit register PWMPD. Whenthe user-specified on-time for a channel would result in a calcu-lated pulse width less than the value specified in the PWMPDregister, then the PWM outputs for that channel would be set to

full off (0%) and its prime to full on (100%). This is valid forA, AP, B, BP, C and CP. This feature would be used in an en-vironment where the inverters power transistors have a mini-mum switching time. If the user-specified duty cycle wouldresult in a pulse duration shorter than the minimum switchingtime of the transistors, then pulse deletion should be used toprevent this occurrence. With a 10 MHz system clock, the 0 127 range of values in PWMPD yield a range of deadtime valuesfrom 0 s to 12.7 s in 100 ns steps.

External PWM ShutdownThere is an external input pin (STOP) to the PWM timers thatwill disable all six outputs when it goes HIGH. When the STOPpin goes HIGH, the PWM timer outputs will all go HIGHwithin one system clock cycle. When the STOP pin goesLOW, the PWM timer outputs are re-enabled within one systemclock cycle. If external PWM shutdown isnt required, tie theSTOP pin LOW.

VECTOR TRANSFORMATION BLOCK OVERVIEWThe Vector Transformation Block performs both Park andClarke coordinate transformations to control a three-phasemotor (Permanent Magnet Synchronous Motor or InductionMotor) via independent control of the decoupled rotor torqueand flux currents. The Park & Clarke transformations combineto convert three-phase stator current signals into two orthogonalrotor referenced current signals Id and Iq. Id represents the fluxor magnetic field current and Iq represents the torque generat-ing current. The Id and Iq current signals a re used by theprocessors motor torque control algorithm to calculate therequired direct Vd and quadrature Vq voltage components forthe motor. The forward Park and Clarke transformations areused to convert the Vd and Vq voltage signals in the rotor refer-ence frame to three phase voltage signals (U, V, W) in the statorreference frame. These are then scaled by the processor and

written to the ADMC200s PWM registers in order to drive theinverter. The figures below illustrate the Clarke and ParkTransformations respectively.

Iw

Iu

Iv

Iy

Ix

120

120

120

Three-Phase Equivalent Stator Currents Two-Phase Currents

Figure 7. Reverse Clarke Transformation

Iy

Ix

Iq

Id

ROTORREFERENCEFRAME AXIS

90

Rotating Stationary Reference Frame Reference Frame

Figure 8. Reverse Park Transformation

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Vq

Vd

Vy

Vx

90

Stationary Rotating Reference Frame Reference Frame

Figure 9. Forward Park Transformation

V y

V x

W

U

V

120

120

120

Equivalent Three-Phase Stator Two-Phase Voltage Voltage

Figure 10. Forward Clarke Transformation

Operating/Using the Vector Transformation BlockAfter powering up the ADMC200, RESET must be drivenlow for a minimum of two clock cycles to enable vectortransformations.

The vector transformation block can perform either a forward orreverse transformation.

Reverse Transformation is defined by the following operations:(a) Clarke: 3-phase current signals to 2-phase current signals

followed by (b) Park: 2-phase current signals cross multiplied bysin , cos which effectively measures the current componentswith respect to the rotor (stationary) where is the electricalangle of the rotor field with respect to the stator windings.

Forward transformation is defined by the following operations:(a) Park: 2-phase voltage signals cross multiplied by sin , cos followed by (b) Clarke: 2-phase to 3-phase voltage signalconversion.

In order to provide maximum flexibility in the target system, theADMC200 operates in an asynchronous manner. This meansthat the functional blocks (analog input, reverse transformation,forward transformation and PWM timers) operate indepen-dently of each other. The reverse and forward vector transfor-

mation operations cannot occur simultaneously. All vectortransformation registers, except for RHO/RHOP, are twoscomplement. RHO/RHOP are unsigned ratios of 360 . For ex-ample, 45 would be 45/360 2 12.

Performing a Reverse TransformationA reverse transformation is initiated by writing to the reverserotation angle register RHO and operates on the values in thePHIP1, PHIP2 and PHIP3 registers. When the reverse trans-formation is in 2/3 mode, PHIP1 is calculated from PHIP2 andPHIP3. This is used in systems where only two phase currentsare measured. The reverse transformation 2/3 mode is set byclearing Bit 10 in the SYSCTRL register and is the defaultmode after RESET .

In order to perform a reverse transformation, first write to thePHIP2 and PHIP3 registers, and to the PHIP1 register if not in2/3 mode. Then initiate the transformation by writing the re-verse rotation angle to the RHO register.

The reverse rotation will be completed in 37 system clock cyclesafter the rotation is initiated. If Bit 6 of the system control reg-ister is set, then an interrupt will be generated on completion.When an interrupt occurs, the user must check Bit 1 of theSYSSTAT register to determine if the vector transformationblock was the source of the interrupt.

During the vector transformation, the vector transformationregisters must not be written to or the vector rotation results willbe invalid.

Reverse Clarke TransformationThe first operation is the Clarke transformation in which thethree phase motor current signals (I u, I v, I w) are converted tosine and cosine orthogonal signals (I x and I y). These signalsrepresent the equivalent currents in a two-phase ac machine andis the signal format required for the Park rotation. The three-phase input signals are of the form:

PHIP1 I u = I s cosPHIP2 I v = I s cos ( + 120)PHIP3 I w = I s cos ( + 240)and the Park rotation requires inputs in the form I s cos andIs sin , therefore we need to generate I s sin .

This is calculated from:

IY I s sin =1

3 ( I s cos ( + 240) I s cos ( +120))

After the reverse transform, registers I x and I y contain the 2-phase input current information.

In the case where 2 of 3-phase information (PHIP2/3 only) is

provided, then PHIP1 will be derived from the simple fact thatall sum to zero. This value is then placed in the IX register.

IX = I x = I s cos = I s cos ( + 120) I s cos ( + 240)

Reverse Park RotationIX/IY are then processed together with the digital angle (RHO) by a Park rotation. If the input signals are I x and I y,then the rotation can be described by:

ID I d = I x cos + I y sin IQ I q = I y sin + I y cos

where ID and IQ are the outputs of the Park rotation.

Cos and sin are required for the Park rotation, and are cal-culated internally.

Substituting for I x and I y in the above yields:

ID I d = I s cos cos + I s sin sin = I s cos ( )IQ I q = I s sin cos I s cos sin = I s sin ( )Performing a Forward TransformationIn order to perform a forward rotation, write values to the VDand VQ registers and then initiate the transformation by writingthe rotation angle to the register RHOP. The forward transfor-mation will only operate correctly when Bit 10 in theSYSCTRL register is set (i.e., in 3/3 mode).

The forward rotation will be completed in 40 system clockcycles after the rotation is initiated. If Bit 6 of the system con-trol register is set, then an interrupt will be generated on

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completion. When an interrupt occurs, the user must check Bit1 of the system status register, SYSSTAT, to determine if thevector transformation block was the source of the interrupt.

During the vector transformation, the transformation registersmust not be written to or the vector rotation results will be invalid.

Forward Park Rotation

If the input signals are represented by Vd and Vq, then thetransformation can be described by:

VX Vx = V d cos Vq sin VY Vy = V d sin + V q cos

where V x and V y are the outputs of the Park Rotation, and arethe inputs to the reverse Clarke transformation.

Forward Clarke Transformation (2 to 3 Phase)The second operation to be applied to the above results, is theForward Clarke Transformation where 2 phase (stator) voltagesignals are converted to 3 phase (stator) voltage signals.

For the inverse Clarke transform we require three phase out-puts of the form below:

PHV1 V cos PHV2 V cos ( + 120)PHV3 V cos ( + 240)

We have two quadrature voltages (V cos and V sin ) available.

PHV2 V cos ( + 120) =

1

2 V cos 32 V sin

PHV3 V cos ( + 240) = 12 V cos +

32 V sin

INTERRUPT GENERATIONThere are two interrupt sources on the ADMC200 that may beindependently enabled to generate interrupts. The firstinterrupt source is the Analog Input Block, which, if enabled,generates an interrupt at the end of conversion. The second in-terrupt source is the Vector Transformation Block, which,if enabled, generates an interrupt at the end of a VectorTransformation.

When a 1 is stored in Bit 7 of the SYSCTRL register, ADCinterrupts are enabled. When a 1 is stored in Bit 6 of theSYSCTRL register, Vector Transformation interrupts are en-abled. Upon a reset of the chip, both bits are set to the defaultcondition, 0, thus disabling all interrupts.

When an enabled interrupt occurs, Bit 11 of the SYSSTATregister becomes a 1. If that interrupt had been an ADC inter-

rupt, Bit 0 of SYSSTAT register would also be set to 1. If thatinterrupt had been a Vector Transformation interrupt, Bit 1 of SYSSTAT would be set to 1. Whenever the SYSSTAT registeris read, these three bits go back to their default state, 0, immedi-ately after their values are loaded onto the data bus. Upon a re-set, these three bits also go to their default state, 0.

The IRQ pin has an open-drain driver, which will drive it low atthe appropriate times, but the user must supply an externalpull-up resistor to bring the node back high when it is not beingpulled low.

The IRQ pin operates in one of two modes, edge mode or levelmode. In edge mode, when an enabled interrupt occurs, the

IRQ pin will be driven low for one system clock period. In levelmode, when an enable interrupt occurs, the IRQ pin will bedriven low, and will remain low until the SYSSTAT register isread. The combination of level mode and the open-drain driverallows multiple interrupt sources in an application to drive asingle interrupt input line on the host DSP or microprocessor.Edge mode or level mode is determined with Bit 8 of theSYSCTRL register. Edge mode (0) is the default; a 1 in this bitwill put the IRQ pin into level mode.

The recommended method of using the interrupt generationcapability is to set edge or level mode, enable the appropriateinterrupts, and then monitor the IRQ line. After the IRQ pingoes low, the SYSSTAT register of the ADMC200 should beread, (1) to determine if it was this chip that caused the inter-rupt, if other lines are wired together with this IRQ pin, and (2)if it was this chip, to determine if it was generated by the AnalogInput Block or the Vector Transformation Block. Once thisis done, the appropriate interrupt handling routine may beexecuted.

APPLICATION NOTE LIST1. AN-407 AC Motor Control Experiments Using the ADMC200 Evaluation Board

2. AN-408 AC Motor Control Using the ADMC200 MotionCoprocessor

3. AN-409 Advanced Motor Control Techniques Using the ADMC200 Motion Coprocessor

POWER SUPPLY CONNECTIONS AND SETUPThe nominal positive power supply level (V DD ) is +5 V 5%.The positive power supply V DD should be connected to allADMC200 V DD pins (10, 19, 26, 39, 44, 59). The SGND pin(32) and both AGND pins (27, 28) should be star point con-nected at a point close to the AGND pins of the ADMC200.

The DGND pins (20, 40, 41, 42, 43, 46, 56, 57, 58) shouldalso be connected to AGND pins close to the ADMC200.

Power supplies should be decoupled at the power pins using a0.1 F capacitor. A 220 nF capacitor must also be connected asclose as possible between REFIN (Pin 33) and SGND (Pin 32).In addition, the IRQ requires a 15 K pull-up to the V DD supply.

DSP/CONTROLLER INTERFACEThe ADMC200 has a 12 bit bidirectional parallel port for inter-facing with Analog Devices ADSP-2100 DSP family or micro-controllers/microprocessors.

The ADMC200 coprocessor is designed to be conveniently in-terfaced to ADIs family of fixed-point DSPs. Figures 11 and 12

show the interfacing between the ADMC200 and the ADSP-2101/2105/2115, ADSP-2171, ADSP-2181, TMS320C2XDSPs. In the case of the TMS320C2X, some glue logic is re-quired to decode the RD/ WR lines and invert the CLKOUT1signal.

The ADSP-2101/2105/2115 CLKOUT frequency equals thecrystal/clock frequency of its CLKIN. This signal (CLKOUT)can be used to directly drive the CLK line (Pin 21) on theADMC200. The ADMC200 coprocessor can be operated witha clock frequency between the range of 6.25 MHz and 25 MHz.If the clock frequencies are greater than 12.5 MHz, then it isnecessary to internally divide down the external clock to derivethe ADMC200s system clock (via SYSCTRL register).

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In the case of the ADSP-2171/2181, the system clock is inter-nally scaled; a 10 MHz system clock will derive a 20 MHzCLKOUT. In the case of the TMS320C2X, the CLKOUT1signal is derived from the system clock divided by a factor of 4;consequently a 50 MHz TMS320C25-50 will derive a 12.5 MHzCLKOUT1 for use by the ADMC200.

Note: A pull-up resistor is required on the IRQ (Pin 18) outputfrom the ADMC200. The STOP (Pin 47) must be tied low if not in use.

SYSTEM CLOCK FREQUENCYThe nominal range of the input clock for the ADMC200 is6.25 MHz to 25 MHz. The external CLK frequency can be in-ternally divided down by 2 by writing to Bit 5 of the SYSCTRL register. If the external CLK is faster than 12.5 MHz then it isnecessary to internally divide it down.

REGISTER ADDRESSINGFour address lines (A0 through A3) are used in conjunctionwith the control lines ( CS , WR , RD ,) to select registers 0

through 15. The CS and RD control lines are active low. Theregisters are given symbolic names.

Table II.

Pin Function

CS Enables the ADMC200 register interface(connect via chip select logic-active low)

RD Places data from the internal register onto thedata bus

WR Loads the internal register with data on thedata bus on its positive edge

EN

ADDRESSDECODE

VDD

DMS

IRQ2

RD

WR

CLKOUT

D0D23

A0A13

ADSP2101/ADSP2105/ADSP211520MHz

ADSP218110MHz

ADSP217110MHz

CS

IRQ

RD

WR

CLK

D0D11*

A0A3

ADMC200

ADDRESS BUS

DATA BUS

*NOTE: BY MAPPING THE ADMC200 DATA BUS TO THE TWELVE HIGHEST BITS OF THE ADSP DATA BUS, FULL-SCALE OUTPUTS FROM THE ADC CAN BE REPRESENTED BY 1.0 IN FIXED POINT ARITHMETTIC.

Figure 11. ADI Digital Signal Processor/Microcomputer

EN

ADDRESSDECODE

VDD

IS

INTn

STRB

R/W

CLKOUT1

D0D15

A0A15

TMS320C20

TMS320C25-50TMS320C25

CS

IRQ

RD

WR

CLK

D0D11

A0A3

ADMC200

ADDRESS BUS

DATA BUS

Figure 12. TI Second-Generation Devices TMS320C20/ C25/C2550

Table III. Write Registers

Name A 3 A2 A1 A0 Register Function

RHO 0 0 0 0 Load RHO ( ) and Start Reverse TransformPHIP1/VD 0 0 0 1 Reverse Rotation Direct Input/Forward Direct InputPHIP2/VQ 0 0 1 0 Reverse Rotation Direct Input/Forward Direct InputPHIP3 0 0 1 1 Reverse Rotation Direct InputRHOP 0 1 0 0 Load RHOP( ) and Start Forward TransformPWMTM 0 1 0 1 PWM Master Switching PeriodPWMCHA 0 1 1 0 PWM Channel A On-TimePWMCHB 0 1 1 1 PWM Channel B On-TimePWMCHC 1 0 0 0 PWM Channel C On-TimePWMDT 1 0 0 1 PWM Programmable Deadtime (7-Bit Register)PWMPD 1 0 1 0 PWM Pulse Deletion Value (7-Bit Register)

1 0 1 1 Reserved1 1 0 0 Reserved

SYSCTRL 1 1 0 1 System Control1 1 1 0 Reserved1 1 1 1 Reserved

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