Ch. 2 Combinational Logic Circuits

2005. 3. 15• Binary Logic and Gates• Boolean Algebra• Standard Forms : Minterms and Maxterms• Map Simplification• Map Manipulation• NAND and NOR Gates• Exclusive-OR Gates• Integrated Circuits• CMOS Circuits

http://www.ks.ac.kr/~kimbh/lecture2005.html

• Binary Logic and Gates– Binary Logic

• 2개의이산값을취하는 2진변수를다루는수학적논리연산• 논리변수의값 : 0 or 1• 2진변수와관련된기본논리연산 : AND, OR, NOT

– 정의 : page 32– 진리표 : Table 2-1

– Logic Gates• 하나또는그이상의입력신호가출력신호를야기하도록작동하는전자회로

• Graphic symbols : Fig. 2-1

• Graphic symbols : Fig. 2-2

• Boolean Algebra– 논리연산을다루는수학적인논리이론 (영국수학자 George Boole,

1854년)– Basic Identities of Boolean Algebra

• Example : Table 2-2, Fig. 2-3• 부울대수의기본항등식 : Table 2-3• DeMorgan’s Theorem : Table 2-4

• Fig. 2-3

• 부울대수의기본항등식 : Table 2-3

• DeMorgan’s Theorem : Table 2-4

– Algebraic Manipulation• 대수적조작에의한회로의간략화 : Cost Down• Examples

– page 40, Fig. 2-4, Table 2-5– page 40, 41, 42

– Complement of a Function• DeMorgan’s Theorem이용 : Ex. 2-1• Duality principle 이용 : Ex. 2-2

• Standard Forms– Minterms

• 모든변수가보수나보수가아닌상태로한번나타나는논리곱항: Table 2-6

• 최소항의성질 : page 47– n개의부울변수에대해 개의최소항존재, 최소항의값 : 0 ~ ( -1)– 모든부울함수는최소항의논리합으로표현된다.– 함수의보수는원래의함수에포함되지않은최소항을포함한다.– 모든 의최소항을포함하는함수의논리는 1

– Maxterms• 보수나보수가아닌상태의모든 변수를포함하는논리합항 : Table 2-7

2n 2n

2n

– Sum of minterms• Minterm의합의형태로표현한부울함수식 (F=1인경우) : page 46,

Table 2-8( , , ) (0, 2,5,7)F X Y Z m=∑( , , ) (1,3,4,6)F X Y Z m=∑

(0,1,2,4,5), (3,6,7)E m E m= =∑ ∑

– Product of maxterms• Maxterm의곱의형태로표현한부울함수식 (F=0인경우) : page 47,

Table 2-8

– Sum of Products• Fig. 2-5

( , , ) (1,3, 4,6)F X Y Z M=∏

• 3단계, 2단계구현 : Fig. 2-6

– Product of Sums

• Map Simplification– Karnaugh Map ( K-Map) : 부울함수식간략화방법– Two-Variable Map : Figs. 2-8, 2-9, page 53

– Three-variable Map• Example 2-3 : Figs. 2-10, 2-11, page 56

• Fig. 2-12

• Fig. 2-13

• Ex. 2-4 : Fig. 2-14

• Figs. 2-15, 2-16

– Four-Variable Map• Example 2-5 : Figs. 2-17, 2-18, 2-19, page 59

• Fig. 2-19

• Example 2-6 : Fig. 2-20

• Map Manipulation– Essential Prime Implicants : page 62

• 함수의최소항이오직하나의주항에포함될경우, 즉중복없이묶을수있는독립사각형에해당하는함수식

• Example 2-7 : Fig. 2-21

• Example 2-8 : Fig. 2-22

– Nonessential Prime Implicants• 선택규칙 : 가능한주항사이의중복최소화• Example 2-9 : Fig. 2-23

– Product-of-Sums Simplification• Example 2-10 : Fig. 2-24

– Don’t-Care Conditions : page 67, Fig. 2-25

• 다단회로의최적화– Fig. 2-26

– Example 2-12 : Figs. 2-27 (a), (b)

– Example 2-13 : Figs. 2-27 (c), 시간지연감소

• 다른 Gates– 단순 Logic Gates : Fig. 2-28

– 복합 Logic Gates : Fig. 2-29

– NAND Gate만이용 : Fig. 2-30

• Exclusive-OR Gates– Page 79, See Fig. 2-29

0 10 1

( ) ( )

X X X XX X X XX Y X Y X Y X YA B B AA B C A B C

⊕ = ⊕ =

⊕ = ⊕ =

⊕ = ⊕ ⊕ = ⊕⊕ = ⊕⊕ ⊕ = ⊕ ⊕

– Odd Function : 3개이상의변수를가진 XOR• Multiple-Input Odd Functions : Fig. 2-31

• Parity Generation and Checking : Fig. 2-32

• High impedance output– 3-states buffer : Fig. 2-33

– Fig. 2-34

– Transmission gates : Figs. 2-35, 2-36

• Homework #2– 2-3, 2-5, 2-7, 2-8, 2-19, 2-25, 2-33