mf5cm

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TLH5066

MF5Univers

alMonolithicSwitchedC

apacitorFilter

February 1995

MF5 Universal Monolithic Switched Capacitor FilterGeneral DescriptionThe MF5 consists of an extremely easy to use general pur-pose CMOS active filter building block and an uncommittedop amp The filter building block together with an external

clock and a few resistors can produce various second orderfunctions The filter building block has 3 output pins One ofthe output pins can be configured to perform highpass all-

pass or notch functions and the remaining 2 output pinsperform bandpass and lowpass functions The center fre-

quency of the filter can be directly dependent on the clockfrequency or it can depend on both clock frequency andexternal resistor ratios The uncommitted op amp can be

used for cascading purposes for obtaining additional all-pass and notch functions or for various other applications

Higher order filter functions can be obtained by cascadingseveral MF5s or by using the MF5 in conjuction with theMF10 (dual switched capacitor filter building block) The

MF5 is functionally compatible with the MF10 Any of theclassical filter configurations (such as Butterworth Bessel

Cauer and Chebyshev) can be formed

FeaturesY Low costY 14-pin DIP or 14-pin Surface Mount (SO) wide-body

packageY Easy to useY Clock to center frequency ratio accuracy g06%Y Filter cutoff frequency stability directly dependent on

external clock qualityY Low sensitivity to external component variationsY Separate highpass (or notch or allpass) bandpass low-

pass outputsY focQ range up to 200 kHzY Operation up to 30 kHz (typical)Y Additional uncommitted op-amp

Block and Connection Diagrams

TLH50661

All Packages

TLH50662Top View

Order Number MF5CNSee NS Package Number N14A

Order Number MF5CWM

See NS Package Number M14B

C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A

www.agelectronica.com www.agelectronica.c


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Absolute Maximum RatingsIf MilitaryAerospace specified devices are requiredplease contact the National Semiconductor SalesOfficeDistributors for availability and specifications

Supply Voltage (Va b Vb) 14V

Power Dissipation TA e 25C (note 1) 500 mW

Storage Temp 150C

Soldering InformationN Package 10 sec 260CSO Pack age Vapor phase (60 sec) 215C

Infrared (15 sec) 220C

See AN-450 Surface Mounting Methods and Their Effect

on Product Reliability for other methods of soldering sur-face mount devices

Input Voltage (any pin) Vb s Vin s Va

Operating Temp Range TMIN s TA s TMAX

MF5CN MF5CWM 0C s TA s 70C

Electrical Characteristics Va e 5V g 05% Vb e b5V g 05% unless otherwise notedBoldface limitsapply over temperature TMIN s TA s TMAXFor all other limits TA e 25C

Typical T ested Design

Parameter Conditions(Note 6)

Limit Limit Units(Note 7) (Note 8)

Supply Voltage Min 8 V(Va b Vb) Max 14 V

Maximum Supply Current Clock applied to Pin 8 45 60 mANo Input Signal

Clock Filter Output 10 mV

Feedthrough Op-amp Output 10 mV

Filter Electrical Characteristics Va e 5Vg 05% Vb e b5Vg 05% unless otherwise notedBoldfacelimits apply over temperature TMIN s TA s TMAXFor all other limits TA e 25C

Typical Tested Design



Center Frequency Max 30 20 kHzRange (fo) Min 01 02 Hz

Clock Frequency Max 15 10 MHzRange (fCLK) Min 50 10 Hz

Clock to CenterIdeal

Vpin9 e a5V 5011 g 02% 50 11 g 15%Frequency Ratio

Qe10 FCLKe250 kHz

(fCLKfo) Mode 1 Vpin9 e b5V 10004 g 02% 10004 g 15%

FCLKe500 kHzfCLKfoTemp Vpin9 e a5V g10 ppmCCoefficient (501 CLK ratio)

Vpin9 e b5V g20 ppmC(1001 CLK ratio)

Q Accuracy (Max)Ideal

Vpin9 e a5V g10 %(Note 2)

Qe10 FCLKe250 kHz

Mode 1 Vpin9 e b5V g10 %FCLKe500 kHz

Q Temperature Vpin9 e a5V b200 ppmCCoefficient (501 CLK ratio)

Vpin9 e b5V b70 ppmC(1001 CLK ratio)

DC Lowpass Gain Mode 1g02 dB

Accuracy (Max) R1 e R2 e 10 kX

DC Offset Vos1 g50 mV

Voltage (Max) Vos2 Vpin9 e a5V b185 mV

Vos3 (501 CLK ratio) a115 mV

(Note 3) Vos2 Vpin9 e b5V b310 mV

Vos3 (1001 CLK ratio) a240 mV

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Filter Electrical Characteristics Va e 5Vg 05% Vb e b5Vg 05% unless otherwise noted Boldfacelimits apply over temperature TMIN s TA s TMAXFor all other limits TA e 25C (Continued)




Output BP LP pins RL e 5 kX g40 g38 VSwing (Min) NAPHP pin RL e 35 kX g42 g38 V

Vpin9e a5V 83 dB

Dynamic Range (501 CLK ratio)(Note 4) Vpin9e b5V 80 dB

(1001 CLK ratio)

Maximum Output Short Circuit Source 20 mACurrent (Note 5) Sink 30 mA

OP-AMP Electrical Characteristics Va e a5V g05% Vb e b5V g05% unless other noted Bold-face limits apply over temperature TMIN s TA s TMAXFor all other limits TA e 25C




Gain Bandwidth Product 25 MHz

Output Voltage Swing (Min) RL e 35 kX g42 g38 V

Slew Rate 70 Vms

DC Open-Loop Gain 80 db

Input Offset Voltage (Max) g50 g20 mV

Input Bias Current 10 pA

Maximum OutputSource

20 mAShort CircuitCurrent (Note 5) Sink 30 mA

Logic Input Characteristics Boldface limits apply over temperature TMIN s TA s TMAXAll other limits TA e 25 C



Limit Limit Units(Not e 7) (Not e 8)

CMOS Clock Min Logical 1 30 VInput Input Voltage Va e a5V Vb e b5V

Max L og ic al 0 VLSh e0V b30 V

Input VoltageMin Logical 1 80 VInput Voltage Va e a10V Vb e 0V

Max L og ic al 0 VLSh e a5V 20 VInput Voltage

TTL Clock Min Logical 1 20 VInput Input Voltage Va e a5V Vb e b5V

Max L og ic al 0 VLSh e 0V 08 VInput Voltage

Note 1 The typical junction-to-ambient thermal resistance (iJA) of the 14 pin N package is 160CW and 82CW for the M package

Note 2 The accuracy of the Q value is a function of the center frequency (fo) This is illustrated in the curves under the heading Typical Performance

Characteristics

Note 3 Vos1 V os2 and Vos3 refer to the internal offsets as discussed in the Application Information section 34

Note 4For g5V supplies the dynamic range is referenced to 282V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200mV rms for

the MF5 with a 501 CLK ratio and 280 mV rms for the MF5 with a 1001 CLK ratio

Note 5The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to

the negative supply The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting

that output to the positive supply These are the worst case conditions

Note 6 Typicals are at 25C and represent most likely parametric normNote 7 Guaranteed and 100% tested

Note 8 Guaranteed but not 100% tested These limits are not used to calculate outgoing quality levels

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Pin DescriptionLP(14) BP(1) The second order lowpass bandpassNAPHP(2) and notchallpasshighpass outputs The

LP and BP outputs can typically sink 1 mA

and source 3 mA The NAPHP outputcan typically sink 15 mA and source 3

mA Each output typically swings to within1V of each supply

INV1(3) The inverting input of the summing opamp of the filter This is a high impedanceinput but the non-inverting input is

internally tied to AGND making INV1behave like a summing junction (lowimpedance current input)

S1(4) S1 is a signal input pin used in the allpassfilter configurations (see modes 4 and 5)

The pin should be driven with a sourceimpedance of less than 1 kX If S1 is notdriven with a signal it should be tied to

AGND (mid-supply)SA(5) This pin activates a switch that connects

one of the inputs of the filters secondsummer to either AGND (SA tied to Vb)

or to the lowpass (LP) output (SA tied toVa) This offers the flexibility needed forconfiguring the filter in its various modes

of operation50100(9) This pin is used to set the internal clock to

center frequency ratio (fCLKfo) of thefilter By tying the pin to V a an fCLKforatio of about 501 (typically 5011 g

02%) is obtained Tying the 50100 pin toeither AGND or Vb will set the fCLKforatio to about 1001 (typically 10004 g

02%)AGND(11) This is the analog ground pin This pin

should be connected to the systemground for dual supply operation or biased

to mid-supply for single supply operationFor a further discussion of mid-supplybiasing techniques see the Applications

Information (Section 32) For optimumfilter performance a clean ground must

be provided

Va(6) Vb(10) These are the positive and negativesupply pins The MF5 will operate over atotal supply range of 8V to 14V

Decoupling the supply pins with 01 mFcapacitors is highly recommended

CLK(8) This is the clock input for the filter CMOSor TTL logic level clocks can be

accomodated by setting the L Sh pin tothe levels described in the L Sh pindescription For optimum filter

performance a 50% duty cycle clock isrecommended for clock frequenciesgreater than 200 kHz This gives each op

amp the maximum amount of time tosettle to a new sampled input

L Sh(7) This pin allows the MF5 to accommodateeither CMOS or TTL logic level clocks Fordual supply operation (ie g5V) a CMOSor TTL logic level clock can be accepted ifthe L Sh pin is tied to mid-supply (AGND)

which should be the system groundFor single supply operation the L Sh pin

should be tied to mid-supply (AGND) for aCMOS logic level clock The mid-supplybias should be a very low impedance

node See Applications Information forbiasing techniques For a TTL logic levelclock the L Sh pin should be tied to V b

which should be the system groundINV2(12) This is the inverting input of the

uncommitted op amp This is a very highimpedance input but the non-inverting

input is internally tied to AGND makingINV2 behave like a summing junction(low-impedance current input)

Vo2(13) This is the output of the uncommitted opamp It will typically sink 15 mA and

source 30 mA It will typically swing towithin 1V of each supply

Typical Performance Characteristics

Deviation ofFCLK

Fovs No minal Q Deviati on of

FCLK

Fovs Nominal Q

OPAMP Output VoltageSwing vs Temperature

TLH50663

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Typical PerformanceCharacteristics(Continued)

Supply Current vs Temperature

TLH50664

10 Definitions of TermsfCLK the frequency of the external clock signal applied to

pin 8

fo center frequency of the second order function complexpole pair fois measured at the bandpass output of the MF5

and is the frequency of maximum bandpass gain (Figure 1)

fnotch the frequency of minimum (ideally zero) gain at thenotch output

fz the center frequency of the second order complex zero

pair if any If fzis different from foand if Qzis high it can be

observed as the frequency of a notch at the allpass output(Figure 10)

Q quality factor of the 2nd order filter Q is measured at

the bandpass output of the MF5 and is equal to fodivided bythe b3dB bandwidth of the 2nd order bandpass filter (Fig-

ure 1 ) The value of Q determines the shape of the 2ndorder filter responses as shown in Figure 6

Qzthe quality factor of the second order complex zero pair

if any Qz is related to the allpass characteristic which iswritten

HAP(s) e

HOAP s2 bs0oQz

a 0o2Js2 a

s0oQ

a 0o2

where Qz e Q for an all-pass response

HOBP the gain (in VV) of the bandpass output at f e fo

HOLPthe gain (in VV) of the lowpass output as fx 0 Hz

(Figure 2)

HOHP the gain (in VV) of the highpass output asfx fclk2 (Figure 3)

HONthe gain (in VV) of the notch output as fx 0 Hz and

as fx fclk2 when the notch filter has equal gain aboveand below the center frequency (Figure 4) When the low-

frequency gain differs from the high-frequency gain as in

modes 2 and 3a (Figures 11 and 8 ) the two quantities be-low are used in place of H ON

HON1 the gain (in VV) of the notch output as fx0 Hz

HON2 the gain (in VV) of the notch output as fxfclk2

(a) TLH50665 (b) TLH50666

HBP(s) e HOBP

0oQ

s

s2 as0o

Qa 0o2

Q e fo

fH b fL fo e 0fLfH

fL e fo b1

2Qa 0

1

2Q J2

a 1 JfH e fo

1

2Qa 0

1

2Q J2

a 1 J0o e 2qfo

FIGURE 1 2nd-Order Bandpass Response

(a) TLH50667 (b) TLH50668

HLP(s) e

HOLP0o2

s2 as0o

Qa 0o2

fc e fo c 01 b 1

2Q2 J a 01 b 1

2Q2 J2

a 1

fp e fo 01 b 1

2Q2

HOP e HOLP c 1

1

Q 01 b 1

4Q2

FIGURE 2 2nd-Order Low-Pass Response

(a) TLH50669

FIGURE 3 2nd-Order High-Pass Response

(b) TLH506610

HHP(s)e HOHPs2

s2 as0o

Qa0o2

fcefoc 0 1b 12Q2 J a0 1b 12Q2 J 2a1 (b1

fp e fo c

01 b

1

2Q2

(

b1

HOP e HOHP c 1

1

Q 01 b 1

4Q2

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10 Definition of Terms(Continued)

TLH506611

(a)TLH506612

(b)

HN(s) e HON(s2 a 0o2)

s2 as0o

Qa 0o2

Q e fo

fH b fL fo e 0fLfH

fL e fo b1

2Qa 0

1

2Q J2

a 1 JfH e fo

1

2Qa

0 1

2Q J2

a 1 J

FIGURE 4 2nd-Order Notch Response

TLH506613

(a)

TLH506614

(b)

HAP(s) e

HOAP s2 bs0o

Qa 0o2 J

s2 as0o

Qa 0o2

FIGURE 5 2nd-Order All-Pass Response

(a) Bandpass (b) Low-Pass (c) High-Pass

(d) Notch (e) All-Pass

TLH506615

FIGURE 6 Responses of various 2nd-order filters

as a function of Q Gains and center frequenciesare normalized to unity

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20 Modes of OperationThe MF5 is a switched capacitor (sampled data) filter Tofully describe its transfer functions a time domain approachis appropriate Since this is cumbersome and since the

MF5 closely approximates continuous filters the followingdiscussion is based on the well known frequency domain

Each MF5 can produce a full 2nd order function See Table

1 for a summary of the characteristics of the various modesMODE 1 Notch 1 Bandpass Lowpass Outputs

fnotch e fo(See Figure 7)

fo e center frequency of the complex pole pair

efCLK

100or

fCLK

50

fnotch e center frequency of the imaginary zero pair e fo

HOLP e Lowpass gain (as fx 0) e bR2

R1

HOBP e Bandpass gain (at f e fo) e bR3

R1

HON e Notch output gain asfx 0

fx fCLK2 ( e

bR2

R1

Q e fo

BWe

R3

R2

BW e the b3 dB bandwidth of the bandpass output

Circuit dynamics

HOLP eHOBP

Q

or HOBP e HOLP c Q e HON c Q

HOLP(peak) j Q c H OLP (for high Qs)

MODE 1a Non-Inverting BP LP (See Figure 8)

fo ef CLK

100or

fCLK

50

Q eR3

R2

HOLP e b1 HOLP(peak) j Q c H OLP (for high Qs)

HOBP1 e b

R3

R2

HOBP2 e 1 (non-inverting)

Circuit dynamics HOBP1 e Q

Note VIN should be driven from a low impedance (k1 kX)

TLH506616

FIGURE 7 MODE 1

TLH506617

FIGURE 8 MODE 1a

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20 Modes of Operation(Continued)

MODE 2 Notch 2 Bandpass Lowpass fnotchkfo

(See Figure 9)

fo e center frequency

efCLK

100 0R2

R4a 1 or

fCLK

500R2

R4a 1

fnotch e fCLK

100or f

CLK

50

Q e quality factor of the complex pole pair

e0R2R4 a 1

R2R3

HOLP e Lowpass output gain (as fx 0)

e b R2R1

R2R4 a 1

HOBP e Bandpass output gain (at f e f o) e bR3R1

HON1 e Notch output gain (as fx 0)

e b R2R1

R2R4 a 1

HON2 e Notch output gain as fx

fCLK

2 J e bR2R1Filter dynamics HOBP e Q0HOLPHON

2

e Q0HON1

HON2

MODE 3 Highpass Bandpass Lowpass Outputs

(See Figure 10)

fo ef CLK

100c 0

R2

R4or

fCLK

50c 0

R2

R4

Q e quality factor of the complex pole pair

e

0R2R4

c R3R2

HOHP e Highpass gain as fxfCLK

2 J e bR2

R1

HOBP e Bandpass gain (at f e f o) e bR3

R1

HOLP e Lowpass gain (as fx 0) e bR4

R1

Circuit dynamicsR2

R4e

HOHP

HOLP HOBP e 0HOHP c HOLP c Q

HOLP(peak) j Q c H OLP (for high Qs)

HOHP(peak) j Q c H OHP (for high Qs)

TLH506618

FIGURE 9 MODE 2

TLH506619

FIGURE 10 MODE 3

In Mode 3 the feedback loop is closed around

the input summing amplifier the finite GBW prod-

uct of this op amp causes a slight Q enhance-

ment If this is a problem connect a small capaci-

tor (10 pF100 pF) across R4 to provide some

phase lead

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20 Modes of Operation (Continued)

MODE 3a HP BP LP and Notch with External Op amp(SeeFigure 11)

fo efCLK

100c 0

R2

R4or

fCLK

50c 0

R2

R4

Q e

0

R2

R4

cR3

R2

HOHP e bR2

R1

HOBP e bR3

R1

HOLP e bR4

R1

fn e notch frequency ef CLK

100 0Rh

Rlor

fCLK

500Rh

Rl

Hon e gain of notch at f efoe Q R g

RlHOLPb

Rg

RhHOHPJ

Hn1 e gain of notch (as fx 0) eR g

Rlc HOLP

Hn2 e gain of notch as fxfCLK

2 J e bRg

Rhc HOHP

MODE 4 Allpass Bandpass Lowpass Outputs (See

Figure 12)

fo e center frequency

efCLK

100or

fCLK

50

fzecenter frequency of the complex zero pairjfo

Q e fo

BWe

R3

R2

Qz e quality factor of complex zero pair eR3

R1

For AP output make R1 e R2

HOAP e Allpass gain at 0 k f kfCLK

2 J e bR2

R1e b1

HOLP e Lowpass gain (as fx 0)

e b R2

R1a 1J e b2

HOBP e Bandpass gain (at f e fo)

e bR3

R21 aR2

R1J e b2 R3

R2JCircuit dynamics HOBP e (HOLP) c Q e (H OAP a 1) Q

Due to the sampled data nature of the filter a slight mismatch of fz and fooccurs causing a 04 dB peaking around fo of the allpass filter amplitude

response (which theoretically should be a straight line) If this is unaccept-

able Mode 5 is recommended

TLH506620

FIGURE 11 MODE 3a

TLH506621

FIGURE 12 MODE 4

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20 Modes of Operation(Continued)

MODE 5 Numerator Complex Zeros BP LP(See Figure 13)

fo e 01 aR2

R4c

fCLK

100or01 a

R2

R4c

fCLK

50

fz e

0

1 bR1

R4

cfCLK

100

or

0

1 bR1

R4

cfCLK

50

Q e 01 a R2R4 cR3

R2

Qz e 01 b R1R4 cR3

R1

H0z1 e gain at CZ output (as fx0 Hz)e

bR2 (R4bR1)

R1 (R4aR2)

H0z2 e gain at CZ output as fx

fCLK

2 J ebR2

R1

HOBP eb eR2

R1a 1J c

R3

R2

HOLP eb R2 a R1

R2 a R4J cR4

R1

MODE 6a Single Pole HP LP Filter (See Figure 14)

fc e cutoff frequency of LP or HP output

eR2

R3

fCLK

100or

R2

R3

fCLK

50

HOLP

e bR3

R1

HOHP e bR2

R1

MODE 6b Single Pole LP Filter (Inverting and Non-Inverting) (See Figure 15)

fc e cutoff frequency of LP outputs

jR2

R3

fCLK

100or

R2

R3

fCLK

50

HOLP1e 1 (non-inverting)

HOLP2e b

R3

R2

TLH506622

FIGURE 13 MODE 5

TLH506623

FIGURE 14 MODE 6a

TLH506624

FIGURE 15 MODE 6b

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20 Modes of Operation (Continued)TABLE I Summary of Modes Realizable filter types (eg low-pass) denoted by asterisks Unless otherwise noted

gains of various filter outputs are inverting and adjustable by resistor ratios

Mode BP LP HP N AP Number of Adjustable

Notesresistors fCLKfo

1

3 No

(2) May need input buf-

1a HOBP1eb Q HOLPea 1 2 No fer Poor dynamics

HOBP2e a1 for high Q

Yes (above

2 3 fCLK50 orfCLK100)

Universal State-

3 4 Yes Variable Filter Bestgeneral-purpose mode

As above but also

3a 7 Yes includes resistor-tuneable notch

Gives Allpass res-

4

3 No ponse with HOAPeb1

and HOLPeb2

Gives flatter allpass

5 4 response than aboveif R1eR2e002R4

6a 3 Single pole(2)

6b HOLPea 1 2 Single pole

HOLP2ebR3

R2

30 Applications InformationThe MF5 is a general-purpose second-order state variable

filter whose center frequency is proportional to the frequen-cy of the square wave applied to the clock input (f CLK) Byconnecting pin 9 to the appropriate DC voltage the filter

center frequency fo can be made equal to either fCLK100or fCLK50 focan be very accurately set (within g 06%) by

using a crystal clock oscillator or can be easily varied overa wide frequency range by adjusting the clock frequency Ifdesired the fCLKfo ratio can be altered by external resis-

tors as in Figures 9 10 11 13 14 and 15 The filter Q andgain are determined by external resistors

All of the five second-order filter types can be built using the

MF5 These are illustrated in Figures 1 through 5along withtheir transfer functions and some related equations Figure

6 shows the effect of Q on the shapes of these curvesWhen filter orders greater than two are desired two or moreMF5s can be cascaded The MF5 also includes an uncom-

mitted CMOS operational amplifier for additional signal pro-cessing applications

31 DESIGN EXAMPLE

An example will help illustrate the MF5 design procedureFor the example we will design a 2nd order Butterworthlow-pass filter with a cutoff frequency of 200 Hz and a pass-

band gain of b2 The circuit will operate from a g5V powersupply and the clock amplitude will be g5v (CMOS) levels)

From the specifications the filter parameters are

foe200 Hz HOLPeb2 and for Butterworth responseQe0707

In section 20 are several modes of operation for the MF5each having different characteristics Some allow adjust-

ment of fCLKfo others produce different combinations offilter types some are inverting while others are non-invert-

ing etc These characteristics are summarized in Table I Tokeep the example simple we will use mode 1 which hasnotch bandpass and lowpass outputs and inverts the sig-

nal polarity Three external resistors determine the filters Qand gain From the equations accompanying Figure 7

QeR3R2and the passband gain HOLP e bR2R1 Sincethe input signal is driving a summing junction through R1

the input impedance will be equal to R 1 Start by choosing avalue for R1 10k is convenient and gives a reasonable inputimpedance For HOLP e b2 we have

R2 e bR1HOLP e 10k c 2 e 20k

For Q e 0707 we have

R3 e R 2Q e 20k c 0707 e 1414k Use 15k

For operation on g5V supplies Va

is connected to a

5VVb to b5V and AGND to ground The power suppliesshould be clean (regulated supplies are preferred) and

01 mF bypass capacitors are recommended

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30 Applications Information(Continued)

TLH506625

FIGURE 16 2nd-Order Butterworth Low-Pass Filter of Design

Example ForfCLK

f0e 50 Connect Pin 9 to a5V and

Change Clock Frequency to 10 kHz

TLH506626

FIGURE 17 Butterworth Low-Pass Circuit of Example but Designed for Single-Supply Operation

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TLH506627

(a) Resistive Divider withDecoupling Capaciter

TLH506628

(b) Voltage Regulator

TLH506629

(c) Operational Amplifierwith Divider

FIGURE 18 Three Ways of GeneratingVa

2for Single-supply Operation

For a cutoff frequency of 200 Hz the external clock can be

either 10 kHz with pin 9 connected to V a (501) or 20 kHzwith pin 9 tied to AGND or V

b (1001) The voltage on the

Logic Level Shift pin (7) determines the logic threshold forthe clock input The threshold is approximately 2V higher

than the voltage applied to pin 7 Therefore when pin 7 isgrounded the clock logic threshold will be 2V making itcompatible with 0 5 volt TTL logic levels and g5 volt

CMOS levels Pin 7 should be connected to a clean low-im-pedance (less than 1000X) voltage source

The complete circuit of the design example is shown for a1001 clock ratio in Figure 16

32 SINGLE SUPPLY OPERATION

The MF5 can also operate with a single-ended power sup-plyFigure 17 shows the example filter with a single-ended

power supply Va is again connected to the positive powersupply (8 to 14 volts) and V b is connected to ground The

AGNDpin must be tied to Va2 for single supply operation

This half-supply point should be very clean as any noiseappearing on it will be treated as an input to the filter It can

be derived from the supply voltage with a pair of resistorsand a bypass capacitor (Figure 18a) or a low-impedance

half-supply voltage can be made using a three-terminal volt-age regulator or an operational amplifier (Figures 18b and

18c) The passive resistor divider with a bypass capacitor issufficient for many applications provided that the time con-stant is long enough to reject any power supply noise It is

also important that the half-supply reference present a lowimpedance to the clock frequency so at very low clock fre-quencies the regulator or op-amp approaches may be pref-

erable because they will require smaller capacitors to filterthe clock frequency The main power supply voltage should

be clean (preferably regulated) and bypassed with 01mF

33 DYNAMIC CONSIDERATIONS

The maximum signal handling capability of the MF5 like

that of any active filter is limited by the power supply volt-ages used The amplifiers in the MF5 are able to swing towithin about 1 volt of the supplies so the input signals must

be kept small enough that none of the outputs will exceed

these limits If the MF5 is operating on g5 volts for exam-

ple the outputs will clip at about 8Vp-p The maximum inputvoltage multiplied by the filter gain should therefore be less

than 8Vp-p

Note that if the filter has high Q the gain at the lowpass orhighpass outputs will be much greater than the nominal filtergain (Figure 6) As an example a lowpass filter with a Q of10 will have a 20 dB peak in its amplitude response at fo Ifthe nominal gain of the filter H OLPis equal to 1 the gain at

fowill be 10 The maximum input signal at f omust thereforebe less than 800 mVp-p when the circuit is operated on g 5

volt supplies

Also note that one output can have a reasonable small volt-age on it while another is saturated This is most likely for acircuit such as the notch in Mode 1 (Figure 7) The notch

output will be very small at fo so it might appear safe toapply a large signal to the input However the bandpass will

have its maximum gain at foand can clip if overdriven If oneoutput clips the performance at the other outputs will bedegraded so avoid overdriving any filter section even ones

whose outputs are not being directly used AccompanyingFigures 7 through 15 are equations labeled circuit dynam-

ics which relate the Q and the gains at the various outputsThese should be consulted to determine peak circuit gainsand maximum allowable signals for a given application

34 OFFSET VOLTAGE

The MF5s switched capacitor integrators have a higherequivalent input offset voltage than would be found in a

typical continuous-time active filter integrator Figure 19shows an equivalent circuit of the MF5 from which the out-

put dc offsets can be calculated Typical values for theseoffsets are

Vos1 e opamp offset e g5mV

Vos2 e b185mV 501 b310mV 1001

Vos3 e a115mV 501 a240mV 1001

The dc offset at the BP output is equal to the input offset of

the lowpass integrator (Vos3) The offsets at the other out-puts depend on the mode of operation and the resistor ra-

tios as described in the following expressions

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Mode 1 and Mode 4

VOS(N) e VOS1 1

Qa 1 a HOLP J b

VOS3

Q

VOS(BP) e VOS3

VOS(LP) e VOS(N) b VOS2

Mode 1a

VOS(NINVBP) e 1 a 1

QJ VOS1 bVOS3

Q

VOS(INVBP) e VOS3

VOS(LP) e VOS(NINVBP) b VOS2

Mode 2 and Mode 5

VOS(N) e R2

Rpa 1J VOS1 c

1

1 a R2R4

a VOS21

1aR4R2b

VOS3

Q01aR2R4

Rp e R1R2R4

VOS(BP) e VOS3

VOS(LP) e VOS(N) b VOS2

Mode 3

VOS(HP) eVOS2

VOS(BP) eVOS3

VOS(LP) e bR4

R2R2

R3VOS3 a VOS2J a

bR4

R21 aR2

Rp J VOS1 Rp e R1R3R4

TLH506630

FIGURE 19 Block Diagram Showing MF5

Offset Voltage Sources

TLH506631

FIGURE 20 Method for Trimming VOSSee Text Section 34

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For most applications the outputs are AC coupled and DCoffsets are not bothersome unless large signals are applied

to the filter input However larger offset voltages will causeclipping to occur at lower ac signal levels and clipping atany of the outputs will cause gain nonlinearities and will

change fo and Q When operating in Mode 3 offsets can

become excessively large if R2 and R4 are used to makefCLKfosignificantly higher than the nominal value especial-ly if Q is also high An extreme example is a bandpass filterhaving unity gain a Q of 20 and fCLKfo e 250 with pin 9

tied to Vb (1001 nominal) R4R2will therefore be equal to625 and the offset voltage at the lowpass output will be

about a19V Where necessary the offset voltage can beadjusted by using the circuit of Figure 20 This allows adjust-ment of Vos1 which will have varying effects on the different

outputs as described in the above equations Some outputscannot be adjusted this way in some modes however

(Vos(BP) in modes 1a and 3 for example)

35 SAMPLED DATA SYSTEM CONSIDERATIONS

The MF5 is a sampled data filter and as such differs in

many ways from conventional continuous-time filters An im-portant characteristic of sampled-data systems is their ef-fect on signals at frequencies greater than one-half the

sampling frequency (The MF5s sampling frequency is thesame as its clock frequency) If a signal with a frequency

greater than one-half the sampling frequency is applied tothe input of a sampled data system it will be reflected toa frequency less than one-half the sampling frequency

Thus an input signal whose frequency is fs2 a 100 Hz willcause the system to respond as though the input frequency

was fs2 - 100 Hz This phenomenon is known as alias-

ing and can be reduced or eliminated by limiting the inputsignal spectrum to less than fs2 This may in some cases

require the use of a bandwidth-limiting filter ahead of theMF5 to limit the input spectrum However since the clockfrequency is much higher than the center frequency this will

often not be necessary

Another characteristic of sampled-data circuits is that theoutput signal changes amplitude once every sampling peri-

od resulting in steps in the output voltage which occur atthe clock rate (Figure 21) If necessary these can besmoothed with a simple R-C low-pass filter at the MF5

output

The ratio of fCLK to fc (normally either 501 or 1001) willalso affect performance A ratio of 1001 will reduce any

aliasing problems and is usually recommended for wide-band input signals In noise sensitive applications however

a ratio of 501 may be better as it will result in 3 dB loweroutput noise The 501 ratio also results in lower DC offsetvoltages as discussed in 34

The accuracy of the fCLKforatio is dependent on the value

of Q This is illustrated in the curves under the headingTypical Performance Characteristics As Q is changed

the true value of the ratio changes as well Unless the Q is

low the error in fCLKfowill be small If the error is too largefor a specific application use a mode that allows adjustment

of the ratio with external resistors

It should also be noted that the product of Q and fo shouldbe limited to 300 kHz when fo k 5 kHz and to 200 kHz for

fo l 5 kHz

TLH506632

FIGURE 21 The Sampled-Data Output Waveform

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MF5Universa

lMonolithicSwitchedCa

pacitorFilter

Physical Dimensionsinches (millimeters)

SO PackageOrder Number MF5CWM

NS Package Number M14B

Molded Dual-In-Line Package (N)Order Number MF5CN

NS Package Number N14A

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into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the lifefailure to perform when properly used in accordance support device or system or to affect its safety or

with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injuryto the user

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