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T-Spice Pro User Guide Contents Help 14

2 Circuit Analysis Tutorial

�#Introduction 16

�#Example 1: DC Operating Point Analysis 18

�#Example 2: DC Transfer Analysis 24

�#Example 3: Transient Analysis 29

�#Example 4: AC Analysis 34

�#Example 5: Subcircuits 39

�#Example 6: Transient Analysis 45

�#Example 7: Transient Analysis, Powerup Mode 51

�#Example 8: Transient Analysis, Preview Mode 56

�#Example 9: Noise Analysis 61

(continued)

Circuit Analysis Tutorial


�#Example 10: Direct Model Evaluation 64

�#Example 11: Transistor Subthreshold Behavior 68

�#Example 12: MOS Transconductance Amplifier 72

�#Design Examples 76

Circuit Analysis Tutorial Introduction


Introduction

This tutorial provides a hands-on introduction to the integrated components ofthe T-Spice Pro circuit analysis suite.

The tutorial examples follow a standard format, involving sample files (includedupon installation) of various types:

� Schematic data files (.sdb ) describing the circuits to be analyzed ingraphical form, for display and editing by S-Edit™ Schematic Editor.

� Simulation input files (.sp ) describing the circuits to be analyzed in textualform, for editing and simulation by T-Spice™ Circuit Simulator. (Thelistings of input files in this chapter exclude comments.)

� Simulation output files (.out ) containing the numerical results of the circuitanalyses, for manipulation and display by W-Edit™ Waveform Viewer.

T-Spice Pro’s waveform probing feature integrates S-Edit, T-Spice, and W-Editto allow individual points in a circuit to be specified and analyzed (seeWaveform Probing on page 84).

Running the Examples

; Launch T-Spice.

Circuit Analysis Tutorial Introduction


; Use File > Open to open the specified SPICE (.sp) file.

; Use Simulation > Run Simulation to start the simulation.

; In the Run Simulation dialog, under Waveform options choose Show during .

; Click Start Simulation . W-Edit will automatically display the results.

Circuit Analysis Tutorial Example 1: DC Operating Point Analysis


Example 1: DC Operating Point Analysis

DC operating point analysis finds a circuit’s steady-state condition, obtained (inprinciple) after the input voltages have been applied for an infinite amount oftime.

Schematic invert1.sdb

Input invert1.sp

Output invert1.out



Schematic

This CMOS inverter is also used in Example 2: DC Transfer Analysis on page 24and Example 3: Transient Analysis on page 29.



Most of the module instances visible in the “main” schematic — Page0 ofmodule invert1 — have SPICE OUTPUT properties associated with them. Forexample, module Operating point consists of a labeled rectangular (box) symboland the property

[SPICE OUTPUT=.op]

When the schematic is exported as a SPICE netlist (T-Spice input file), thismodule becomes the .op command.

Similarly, module MOSFET_P has the property

[SPICE OUTPUT=M# %{D} %{G} %{S} %{B} ${model} L=${L} W=${W} AD=${AD} PD=${PD} AS=${AS} PS=${PS}]

The variables prefixed by % are replaced by the appropriate node names, and thevariables prefixed by $ are replaced by the appropriate (numerical or string)values (also specified as properties), in the exported netlist. Property valuesspecified when the module is instanced take precedence over default values: inthis case, the default values for the transistor’s width and length are 22u and 2u,respectively, but these are overridden by the specifications W=12u and L=5u atthe level of this module’s instancing in module invert1 .

Input

c2 out Gnd 800ff.include ml2_125.md



m1p out in Vdd Vdd pmos L=5u W=12um1n out in Gnd Gnd nmos L=5u W=8u.opVdd Vdd Gnd 3.0vin in Gnd 1.0.END

A capacitor c2 (signified by the key letter c), connecting nodes out and GND, isdefined, with a capacitance of 800 femtofarads. (Strictly speaking, the capacitorcould be omitted from the circuit for this example, since it does not affect the DCoperation of the inverter.)

The .include command causes T-Spice to read in the contents of the model fileml2_125.md for the evaluation of transistors m1n and m1p . This file (whichmust be in the same directory as invert1.sp ) consists of two .model commands,describing two MOSFET models called nmos and pmos :

.model nmos nmos+ Level=2 Ld=0.0u Tox=225.00E-10+ Nsub=1.066E+16 Vto=0.622490 Kp=6.326640E-05+ Gamma=.639243 Phi=0.31 Uo=1215.74+ Uexp=4.612355E-2 Ucrit=174667 Delta=0.0+ Vmax=177269 Xj=.9u Lambda=0.0+ Nfs=4.55168E+12 Neff=4.68830 Nss=3.00E+10+ Tpg=1.000 Rsh=60 Cgso=2.89E-10+ Cgdo=2.89E-10 Cj=3.27E-04 Mj=1.067+ Cjsw=1.74E-10 Mjsw=0.195



.model pmos pmos+ Level=2 Ld=.03000u Tox=225.000E-10+ Nsub=6.575441E+16 Vto=-0.63025 Kp=2.635440E-05+ Gamma=0.618101 Phi=.541111 Uo=361.941+ Uexp=8.886957E-02 Ucrit=637449 Delta=0.0+ Vmax=63253.3 Xj=0.112799u Lambda=0.0+ Nfs=1.668437E+11 Neff=0.64354 Nss=3.00E+10+ Tpg=-1.000 Rsh=150 Cgso=3.35E-10+ Cgdo=3.35E-10 Cj=4.75E-04 Mj=.341+ Cjsw=2.23E-10 Mjsw=.307

ml2_125.md assigns values to various Level 2 MOSFET model parameters forboth n- and p-type devices. When read by the input file, these parameters areused to evaluate Level 2 MOSFET model equations, and the results are used toconstruct internal tables of current and charge values. Values read or interpolatedfrom these tables are used in the computations called for by the simulation.

Two transistors, m1n and m1p , are defined in invert1.sp . These are MOSFETs,as indicated by the key letter m which begins their names. Following eachtransistor name are the names of its terminals. The required order of terminalnames is: drain–gate–source–bulk. Then the model name (nmos or pmos in thisexample), and physical characteristics such as length and width, are specified.

The .op command performs a DC operating point calculation and writes theresults to the file specified in the Simulate > Start Simulation dialog.

Two voltage sources are defined: Vdd , which sets node Vdd to 3.0 volts relativeto system ground, and vin , which sets node in to 1.0 volt relative to ground.



Output

The output file lists the DC operating point information for the circuit describedby the input file (in addition to comments of various kinds, not shown here).

DC ANALYSISv(out) = 2.9309e+00v(in) = 1.0000e+00v(Vdd) = 3.0000e+000i(Vdd) = -5.8215e-006i(vin) = 0.0000e+000

Circuit Analysis Tutorial Example 2: DC Transfer Analysis


Example 2: DC Transfer Analysis

DC transfer analysis is used to study the voltage or current at one set of points ina circuit as a function of the voltage or current at another set of points. This isdone by sweeping the source variables over specified ranges, and recording theoutput.


Input invert2.sp

Output invert2.out



Schematic



Input

.include ml2_125.mdm1n out in GND GND nmos l=5u w=8um1p out in vdd vdd pmos l=5u w=12uc2 out GND 800ffvdd vdd GND 3.0vin in GND 1.0.dc vin 0 3 0.02 vdd 2 4 0.5.print dc in out

This circuit is identical to that of Example 1: DC Operating Point Analysis onpage 18.

The .dc command, indicating transfer analysis, is followed by a list of sources tobe swept, and the voltage ranges across which the sweeps are to take place.

In this example, vin will be swept from 0 to 3 volts in 0.02 volt increments, andvdd will be swept from 2 to 4 volts in 0.5 volt increments.

The transfer analysis will be performed as follows: vdd will be set at 2 volts andvin will be swept over its specified range; vdd will then be incremented to 2.5volts and vin will be reswept over its range; and so on, until vdd reaches theupper limit of its range.



The .dc command ignores the values assigned to the voltage sources vdd and vinin the voltage source statements, but they must still be declared in thosestatements.

The results for nodes in and out are reported by the .print dc command to thespecified destination.



Output

c:\tspro\tutorial\invert2.out

3 02 52 01 51 00 50 0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vol

t (V

)v(in),0

v(in),1

v(in),2

v(in),3

v(in),4

3.02.52.01.51.00.50.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

vin (V)

Vol

t (V

)

v(out),0

v(out),1

v(out),2

v(out),3

v(out),4

Circuit Analysis Tutorial Example 3: Transient Analysis


Example 3: Transient Analysis

Transient analysis provides information on how circuit elements vary with time.

The basic T-Spice command for transient analysis has three modes. In the defaultmode, the DC operating point is computed, and T-Spice uses this as the startingpoint for the transient simulation. Example 3 illustrates this option. (The othermodes, powerup and preview, are treated in Example 7: Transient Analysis,Powerup Mode on page 51 and Example 8: Transient Analysis, Preview Mode onpage 56.)


Input invert3.sp

Output invert3.out



Schematic



Input

.include ml2_125.mdm1n out in GND GND nmos l=5u w=8um1p out in vdd vdd pmos l=5u w=12uc2 out GND 800ffvdd vdd GND 3.0vin in GND PWL(0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V

300ns+ 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V).tran 2n 600n.print tran in out

This circuit is identical to that of Example 1, except that voltage source vin ,instead of setting the voltage between nodes in and GND at a constant value, heregenerates a piecewise linear waveform input (indicated by the keyword PWL) toin .

The successive “legs” of the waveform are delimited by the corners, whose timesand voltages are specified in the arguments to PWL. Between 0 and 100nanoseconds, the voltage at in is zero; between 100 and 105 nanoseconds, thevoltage is linearly interpolated (ramps up) between 0 and 3; between 105 and 200nanoseconds, the voltage stays at 3; and so on.

The parameters of the device statement that defines vin are continued to the nextline with the + character in the first column.



The .tran command specifies the characteristics of the transient analysis to beperformed: it will last for 600 nanoseconds, with time steps no larger than 2nanoseconds.



Output


550500450400350300250200150100500

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vol

t (V

)v(in)

550500450400350300250200150100500

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Time (ns)

Vol

t (V

)

v(out)

Circuit Analysis Tutorial Example 4: AC Analysis


Example 4: AC Analysis

AC analysis characterizes the circuit’s behavior dependence on small-signalinput frequency. It involves three steps: (1) calculating the DC operating point;(2) linearizing the circuit; and (3) solving the linearized circuit for eachfrequency.

Example 4 involves a standard operational amplifier, consisting of sevenMOSFETs (four n-channel and three p-channel) and two capacitors.

Schematic opamp.sdb

Input opamp.sp

Output opamp.out



Schematic



Input

.include ml2_125.mdmn1 vn1 vbias GND GND nmos l=10u w=6umn2 vm1 in1 vn1 GND nmos l=6u w=6umn3 vf1 in2 vn1 GND nmos l=6u w=6ump1 vm1 vm1 Vdd Vdd pmos l=6u w=6ump2 vf1 vm1 Vdd Vdd pmos l=6u w=6umn4 out vbias GND GND nmos l=10u w=6ump3 out vf1 Vdd Vdd pmos l=6u w=20ucout out GND 2pfccomp vf1 out 2pfvin1 in1 GND 2Vdd Vdd GND 5.0vbias vbias GND 0.8vdiff in2 in1 -0.0007 AC 1 90.ac DEC 5 1 100MEG.print ac vdb(out).print ac vp(out).acmodel opamp1m.out {*}

Three voltage sources (besides Vdd ) are defined.

� vdiff sets the DC voltage difference between nodes in2 and in1 to –0.0007volts; its AC magnitude is 1 volt and its AC phase is 90 degrees.

� vin1 sets node in1 to 2 volts, relative to GND.

� vbias sets node vbias to 0.8 volts, relative to GND.



The .ac command performs an AC analysis. Following the .ac keyword isinformation concerning the frequencies to be swept during the analysis. In thiscase, the frequency is swept logarithmically, by decades (DEC); 5 data points areto be included per decade; the starting frequency is 1 Hz and the endingfrequency is 100 MHz.

The two .print commands write the voltage magnitude (in decibels) and phase (indegrees), respectively, for the node out to the specified file.

The .acmodel command writes the small-signal model parameters and operatingpoint voltages and currents for all circuit devices (indicated by the wildcardsymbol *) to the file opamp1m.out .

This example will generate two output files: opamp1.out , specified by theSimulate > Start Simulation command, and opamp1m.out , specified by the.acmodel command.

Output

The output file opamp1m.out lists small-signal data for all relevant devices.



c:\tspro\tutorial\opamp.out

1E71E61E51E41E310010

150

100

50

0

-50

-100

-150

(dB

)vdb(out)

1E71E61E51E41E310010

150

100

50

0

-50

-100

-150

Frequency (Hz)

(de

g)

vp(out)

Circuit Analysis Tutorial Example 5: Subcircuits


Example 5: Subcircuits

Subcircuit definitions allow arbitrarily complex arrangments of nodes anddevices to be easily reused multiple times in a circuit.

Example 5 uses a NAND gate to illustrate the use of subcircuit definitions andsubcircuit parameters.

Schematic nandgate.sdb

Input nandgate.sp

Output nandgate.out



Schematic



Input

.include ml2_125.md

.subckt NAND in1 in2 out Vdd length=5u nwidth=10u pwidth=10umt1 out in1 n1 GND nmos l='length' w='nwidth'mt2 n1 in2 GND GND nmos l='length' w='nwidth'mt3 out in1 Vdd Vdd pmos l='length' w='pwidth'mt4 out in2 Vdd Vdd pmos l='length' w='pwidth'.endsxnand1 a b outab Vdd NAND nwidth=8u pwidth=12uvvdd Vdd GND 5.0.ic nand1.n1=2Vva a GND PWL(0ns 0V 100ns 0V 105ns 5V 200ns 5V 205ns 0V

+ 300ns 0V 305ns 5V 400ns 5V 405ns 0V 500ns 0V 505ns 5V + 600ns 5V)

vb b GND 5.print tran a outab nand1/n1.op.tran 1n 600n

Subcircuits are defined by blocks of device statements bracketed with the.subckt and .ends commands, and instanced by statements beginning with thekey letter x.

The .subckt command includes the name of the subcircuit being defined(NAND), a list of terminals, and three subcircuit parameters. The terminals do nothave a predefined order, but whatever order is used in the definition must be usedin instances. Parameters can be written in any order in both definition and



instances. Parameter values specified in the definition are used as defaults whennot specified in instances.

Within the subcircuit definition, four MOSFETs are defined in the usual manner(and in these statements the order of terminals is important: drain–gate–source–bulk). Node n1 is the source of transistor mt1 and the drain of transistor mt2 .Subcircuit parameters, enclosed by single quotes, are used in place of numericalvalues.

The subcircuit definition must be terminated by the .ends command. It is acommon mistake to omit this line accidentally.

After the subcircuit is defined, an instance of the subcircuit is created. Theinstance statement begins with the key letter x, but the name of the instance (bywhich it is to be identified in the rest of the input file) is nand1 , not xnand1 .

The list of terminals on the instance statement must have the same order as on thefirst line of the subcircuit definition: a b outab Vdd (instance) corresponds to in1in2 out Vdd (definition). The next argument of the instance statement is theoriginal subcircuit name (NAND).

Two of the default subcircuit parameter values, as originally specified by thedefinition, are overriden by instance-specific assignments. These assignmentsmay appear in any order. The parameter omitted from the instance statement(length ) retains its default value.



Initial conditions on node voltages and currents can be set for the purposes ofcomputing the DC operating point. The .ic command sets node nand1/n1 (that is,node n1 of instance nand1 ) to 2 volts for the duration of the DC operating pointcalculation. When the transient analysis begins, the node will return to a floatingvoltage state.

Voltage source va supplies a PWL (piecewise linear) input waveform to node a.

Two analyses are carried out on this circuit: a DC operating point calculation(.op ) and a transient simulation (.tran ) with a duration of 600 nanoseconds and amaximum timestep of 1 nanosecond.

The .print command reports the results of the simulation for the voltages at nodesa, outab , and nand1/n1 .



Output

c:\tspro\tutorial\nandgate.out

550500450400350300250200150100500

5

4

3

2

1

0

Vol

t (V

)v(a)

550500450400350300250200150100500

5

4

3

2

1

0

Vol

t (V

)

v(outab)

550500450400350300250200150100500

5

4

3

2

1

0

Time (ns)

Vol

t (V

)

v(nand1/nn1)



Example 6: Transient Analysis

Transient analysis on a CMOS static D-latch demonstrates the analog D-latchcharacteristics of a digital circuit. The circuit has four inverters and fourtransmission gates.

Schematic dlatch.sdb

Input dlatch.sp

Output dlatch.out



Schematic



Input

.include ml2_125.md

*** Inverter Subcircuits.subckt invmod1 in out vdd GNDmn out in GND GND nmos l=5u w=8ump out in vdd vdd pmos l=5u w=12u.ends invmod1.subckt invmod2 in out vdd GNDmp vdd in out vdd pmos l=5u w=12umn GND in out GND nmos l=5u w=8u.ends invmod2

*** D Latch Circuitmtg1p n1 phi1 data vdd pmos l=5u w=12umtg1n n1 phi2 data GND nmos l=5u w=8umtg2p n2 phi2 n1 vdd pmos l=5u w=12umtg2n n2 phi1 n1 GND nmos l=5u w=8uxinv1 n1 n3 vdd GND invmod1xinv2 n3 n2 vdd GND invmod2mtg3p n5 phi2 n3 vdd pmos l=5u w=12umtg3n n5 phi1 n3 GND nmos l=5u w=8umtg4p n4 phi1 n5 vdd pmos l=5u w=12umtg4n n4 phi2 n5 GND nmos l=5u w=8uxinv3 n5 Q vdd GND invmod1xinv4 Q n4 vdd GND invmod2cQ Q GND 64ffcdata data GND 32ff



cphi2 phi2 GND 204ffcphi1 phi1 GND 212ffcn4 n4 GND 24ffcn1 n1 GND 96ffcn3 n3 GND 64ffcn2 n2 GND 24ffcn5 n5 GND 96ff* All time specs x5vphi1 phi1 GND bit ({0011} pw=10n off=0.0 on=3.0 rt=1.25n

ft=1.25n)vphi2 phi2 GND bit ({1100} pw=10n off=0.0 on=3.0 rt=1.25n

ft=1.25n)vdata data GND bit ({1000} pw=20n off=0.0 on=3.0 rt=1.25n

ft=1.25n)vvdd vdd GND 3.print tran phi1 phi2 data n1 n3 n5 Q.tran 0.2n 200n

The first three statements beginning with v define voltage sources for custominput waveforms. Following each voltage source name are the names of the inputnodes and the type of waveform. Here, however, not piecewise linear but ratherbit waveforms are used. Following the keyword bit in parentheses are theparameters specifying the waveform characteristics. The four-digit sequence incurly brackets { } specifies the sequence of the wave’s states (either 1, “on,” or 0,“off”). This sequence will be repeated until the simulation is complete. The pulsewidth (pw) is 2 nanoseconds. The off voltage is zero, the on voltage is 3 volts,and the rise (rt ) and fall (ft ) times are each one-quarter of a nanosecond.



Voltage source vdd sets the voltage between power and ground to 3 volts.

The .print command writes the results of the simulation for the voltages at sixnodes to the specified file.

The .tran command instructs T-Spice to perform a 200-nanosecond simulationwhile printing node voltages at least every 0.2 nanoseconds.



Outputc:\tspro\tutorial\dlatch.out

150100500

3210V

olt (

V) v(phi1)

150100500

3

2

1

0

Vol

t (V

)

v(phi2)

150100500

3

2

1

0

Vol

t (V

)

v(data)

150100500

3

2

1

0

Vol

t (V

)

v(a1)

150100500

3

2

1

0

Vol

t (V

)

v(a3)

150100500

3

2

1

0

Vol

t (V

)

v(a5)

150100500

3

1

Time (ns)

Vol

t (V

) v(Q)

Circuit Analysis Tutorial Example 7: Transient Analysis, Powerup Mode


Example 7: Transient Analysis, Powerup Mode

Some circuits do not have a DC steady state or “quiescent” point. Because suchcircuits are constantly fluctuating with time, finding the starting point for theirsimulation is a problem. More precisely, the question is how to define the initialstate of a circuit which has no definite DC steady-state condition. This is done inT-Spice with the powerup option of the .tran command. The powerup optionessentially sets the entire circuit to zero for time equal to zero. As the simulationproceeds, the voltage sources are allowed to ramp up to their specified values.

The ring oscillator is an example of such a time-dependent circuit.

Schematic ring.sdb

Input ring.sp

Output ring.out



Schematic



Input

.include ml2_125.md

.subckt inv in out Vddmt1 out in GND GND nmos l=5u w=8umt2 out in Vdd Vdd pmos l=5u w=12uc2 out GND 800ff.ends invxinv1 a1 a2 Vdd invxinv2 a2 a3 Vdd invxinv3 a3 a4 Vdd invxinv4 a4 a5 Vdd invxinv5 a5 a6 Vdd invxinv6 a6 a7 Vdd invxinv7 a7 a1 Vdd invcinv1 a7 GND 400ffvdd Vdd GND 3.0.print tran a1 a2 a7.tran/powerup 1n 800n

A subcircuit named inv is defined with three terminals. (This inverter isstructurally identical to the one used in Example 1 and Example 4.)

Seven instances of the subcircuit, with names inv1 through inv7 , are definednext. The output of each inverter is connected to the input of the next in the ring.

The powerup option of the .tran command eliminates the DC convergenceproblem for unstable circuits. If the powerup option were not specified, then



T-Spice would try to calculate a DC operating point, which would lead toproblems for this oscillator.



Output

c:\tspro\tutorial\ring.out

7006005004003002001000

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vol

t (V

)v(a1)

7006005004003002001000

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vol

t (V

)

v(a2)

7006005004003002001000

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Time (ns)

Vol

t (V

)

v(a7)

Circuit Analysis Tutorial Example 8: Transient Analysis, Preview Mode


Example 8: Transient Analysis, Preview Mode

Before a lengthy transient simulation is run on a large circuit, the inputwaveforms can be examined using the preview option of the .tran command.This option causes T-Spice to report specified input stimuli only, and to foregosimulation of the remainder of the circuit.

Schematic

In addition to illustrating the preview mode, this simple “wave” circuitshowcases the variety and flexibility of input patterns available to current andvoltage sources in T-Spice.

For a description of this circuit, see Input, below.

Input

r1 n1 GND 2kr2 n2 GND 2kr3 n3 GND 2k

Input wave.sp

Output wave.out



r4 n4 GND 2kr5 n5 GND 2kr6 n6 GND 2kr7 n7 GND 2kr8 n8 GND 2kr9 n9 GND 2kv1 n1 GND pwl (0n 0 100n 0 101n 5 300n 5 301n 0 + 500n 0 680n 5 700n 0 880n 5 900n 0)v2 n2 GND pwl (0n 0 100n 0 101n 1 200n 1 201n 2 300n 2 301n

3+ 400n 3 401n 4 500n 4 501n 5 600n 5 601n 4 + 700n 4 701n 3 800n 3 801n 2 900n 2 901n 1)v3 n3 GND sin (2.5 2.5 30MEG 100n)v4 n4 GND bit ({01010 11011} on=5.0 off=0.0 pw=50n rt=10n

ft=30n)v5 n5 GND bit ({5(01010 5(1))} pw=10n on=5.0 off=0.0).vector bb {n6 n7 n8 n9}vb bb GND bus ({50(Ah) 30(7d4) 20(1000)} pw=5n on=5.0

off=0.0).print tran n1 n2 n3 n4 n5 n6 n7 n8 n9.tran/preview 1n 1u

Nine resistor/node/voltage source combinations, numbered 1 through 9, aredefined. Each resistor has a resistance of 2 kilohms; each voltage source,connected across the corresponding resistor to ground, supplies its characteristicwaveform to the corresponding node.



Two voltage sources, v1 and v2, generate pwl (piecewise linear) inputs. v1produces a single pulse followed by a pair of sawtooth cycles, and v2 produces astaircase waveform which takes 1-volt steps from zero up to 5 volts and backdown to 1 volt.

Voltage source v3 generates a sin (sinusoidal) input. It has an amplitude of 2.5volts, a frequency of 30 MHz, an offset of 2.5 volts from system ground, and atime delay of 100 nanoseconds after the start of the simulation before the wavebegins.

Voltage source v4 generates a bit input. Enclosed in curly brackets { } are twobinary-valued five-bit patterns specifying the waveform. The two patternsalternate in time. The on voltage value is 5.0 volts; the off voltage value is zero.The pulse width (pw), 50 nanoseconds, is the time the wave is either (ramping upand) on, or (dropping down and) off. The rise time (rt ), 10 nanoseconds, is thetime given for the wave to ramp from off to on; and the fall time (ft), 30nanoseconds, the time given for the wave to drop from on to off.

Voltage source v5 generates a repeating bit input. Two distinct patterns are givenagain, but now multiplier factors are included. The wave consists of twoalternating patterns: the first pattern contains five bits, the second is a single bit.The five-bit pattern is followed by five successive repetitions of the single-bitpattern, and this sequence is repeated five times. (The same pattern could bedescribed by {5(3(01) 4(1))} .) The pulse width and on and off voltages are againspecified, but the rise and fall times take default values.



The .vector command defines the bus waveform generated by voltage source vb .The command assigns the bus a name (bb ) and specifies by name the number ofbits the bus waveform will have (four: n6 through n9). The voltage sourcestatement, which contains the bus keyword, specifies waveforms with one ormore patterns, along with pulse width and level information. The patterns can bein binary, hexadecimal, octal, or decimal notation. (For decimal patterns thenumber of lower-order bits to be collected is also given.)

� The first pattern is Ah (hex) = 1010 (binary). Thus, using the names given onthe .vector command, n6=1, n7=0, n8=1, and n9=0. The pattern is repeated50 times (that is, maintained for a time period equal to the pulse widthmultiplied by 50).

� The next pattern is 7d4 — that is, 7 (decimal) = 111 (binary), or, to fourlower-order bits, 0111. So n6=0, n7=1, n8=1, and n9=1. The pattern isrepeated 30 times.

� The last pattern is 1000 (binary), so n6=1, n7=0, n8=0, and n9=0. Thepattern is repeated 20 times.

The .print command writes the results at the output nodes of all nine voltagesources.

The .tran preview command reports the input waveforms in place of running thesimulation.



Outputc:\tspro\tutorial\wave.out

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0Vol

t (V

) v(n1)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n2)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n3)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n4)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n5)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n6)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n7)

0 90 80 70 60 50 40 30 20 10 0

5.0

2.5

0.0

Vol

t (V

) v(n8)

0.90.80.70.60.50.40.30.20.10.0

5.02.50.0

Time (us)

Vol

t (V v(n9)

Circuit Analysis Tutorial Example 9: Noise Analysis


Example 9: Noise Analysis

Real circuits, of course, are never immune from small, “random” fluctuations involtage and current levels. In T-Spice, the influence of noise in a circuit can besimulated and reported in conjunction with AC analysis. The purpose of noiseanalysis is to compute the effect of the noise associated with various circuitdevices on an output voltage or voltages as a function of frequency.

Schematic

For a description of this circuit, see Example 4.

Input

.include ml2_125.mdmn1 vn1 vbias GND GND nmos l=10u w=6umn2 vm1 in1 vn1 GND nmos l=6u w=6umn3 vf1 in2 vn1 GND nmos l=6u w=6u

Schematic opamp2.sdb

Input opamp2.sp

Output opamp2.out



mp1 vm1 vm1 Vdd Vdd pmos l=6u w=6ump2 vf1 vm1 Vdd Vdd pmos l=6u w=6umn4 out vbias GND GND nmos l=10u w=6ump3 out vf1 Vdd Vdd pmos l=6u w=20ucout out GND 2pfccomp vf1 out 2pfvin1 in1 GND 2Vdd Vdd GND 5.0vbias vbias GND 0.8vdiff in2 in1 -0.0007 AC 1 90.ac DEC 5 1 100MEG.noise v(out) vbias.print noise inoise onoise transfer dn(mn1) inoise(tot)

onoise(tot)

Noise analysis is performed in conjunction with AC analysis; if the .ac commandis missing, then the .noise command is ignored. With the .ac command present,the .noise command causes noise analysis to be performed at the samefrequencies: starting at 1 Hz, ending at 100 MHz, 5 data points per decade.

The .noise command takes two arguments: the output at which the effects ofnoise are to be computed, and the input at which the noise can be considered tobe concentrated for the purposes of estimating the equivalent noise spectraldensity.

The .print noise command, with six arguments, writes to the output file 11numbers for each frequency analyzed. Many other options are available.



Outputc:\tspro\tutorial\opamp2.out

1E81E71E61E51E41E3100101

30

20

10

0

Vol

t (uV

/Rt(

Hz)

)inoise(mag)

onoise(mag)

1E81E71E61E51E41E3100101

1.5

1.0

0.5

0.0

Vol

t (V

/V) v(out)/vbias

1E81E71E61E51E41E3100101

400200

0-200-400

Vol

t (m

V/R

t(H

z) dn(mn1,RD)

dn(mn1,RS)

dn(mn1,FN)

1E81E71E61E51E41E3100101

80

60

40

20

0Vol

t (nV

/Rt(

Hz) dn(mn1,ID)

1E81E71E61E51E41E3100101

80

60

40

20

0Vol

t (nV

/Rt(

Hz) dn(mn1,TOT)

1E81E71E61E51E41E3100101

300

200

100

0

Vol

t (kV

/A) dn(mn1,RX)

1E81E71E61E51E41E3100101

1.0

0.5

0.0

Frequency (Hz)

Vol

t (m

V)

inoise(total)

onoise(total)

Circuit Analysis Tutorial Example 10: Direct Model Evaluation


Example 10: Direct Model Evaluation

T-Spice employs two fundamental techniques of simulation: direct modelevaluation and table-based evaluation.

� In direct model evaluation, values are computed as needed from analyticalequations, returning results as accurate as the models used allow.

� In table-based evaluation, tables of values are precomputed from analyticalequations at finite resolution, and needed values are linearly interpolatedfrom stored values. This technique is slightly less accurate, but issignificantly faster.

Table-based evaluation is T-Spice’s default simulation technique. Direct modelevaluation can be explicitly called for, as in Example 10, which repeats thetransient analysis of the inverter of Example 1.


Input invert4.sp

Output invert4.out



Schematic



Input

.options deftables=0

.include ml2_125.mdm1n out in GND GND nmos l=5u w=8um1p out in vdd vdd pmos l=5u w=12uc2 out GND 800ffvdd vdd GND 3.0vin in GND PWL(0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V

300ns+ 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V).tran 2n 600n.print tran in out

This input file is identical to that of Example 1, with one addition: the command.options deftables=0 , which turns off default table generation and causes thecircuit to be simulated by direct evaluation of device models.

Output

Compare invert4.out , obtained using direct model evaluation, to invert1.out ,obtained using internal table-based evaluation. For the inverter or other digitalcircuits there will be only slight differences in the results. For analog circuits,however, there can be greater discrepancies between results from the twoevaluation techniques.




550500450400350300250200150100500

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Vol

t (V

)v(in)

550500450400350300250200150100500

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Time (ns)

Vol

t (V

)

v(out)

Circuit Analysis Tutorial Example 11: Transistor Subthreshold Behavior


Example 11: Transistor Subthreshold Behavior

Modern analog designs are required to meet strict specifications with tighttolerances. Designers therefore need models that can accurately simulatesemiconductor device behavior over all regions of operation.

It has been traditionally difficult to model the operation of MOSFETs in thesubthreshold region, particularly through the transition from subthreshold toabove threshold. This region is of special interest to designers of low-power andadvanced analog designs, in which MOSFETs are sometimes intentionally biasedto operate in this transition region.

In subthreshold, the saturation drain current of a MOSFET is an exponentialfunction of the gate voltage, and the drain current saturates at a drain voltage thatis independent of gate voltage. Well above threshold, the transistor drain currentis a quadratic function of the gate voltage, and the drain current saturates at adrain voltage which is a function of the gate voltage.

T-Spice supports the simulation of MOSFETs in the subthreshold region in thefollowing ways.

� The BSIM3 models (revisions 2 and 3) in the Advanced Model Packageinclude subthreshold characteristics.

� The Maher-Mead model simulates MOSFETs over all regions of operationwith continuous functions for superior accuracy and convergence.



� The T-Spice simulation engine can accurately simulate low-currentoperation without convergence problems even when internal tables are usedfor improved speed.

Example 11 simulates the gate characteristics of a transistor in subthreshold bysweeping its gate voltage while holding its drain voltage fixed.

Input

.include ml5_20.mdmn5 drain gate GND GND nmos l=10u w=6uvdrain drain GND 5vgate gate GND 0.85.dc vgate .5 1.5 0.01.print dc id(mn5).options abstol=1E-14

Voltage source vgate is attached to the gate terminal of the MOSFET mn5 and isswept from 0.5 to 1.5 volts with the .dc command. Voltage source vdrain isattached to the drain terminal with a fixed value of 5 volts, which keeps thetransistor well in saturation. The source and bulk terminals are grounded.

Input trangm.sp

Output trangm.out



The .print dc command reports the current through the drain terminal of mn5.

The .options abstol command changes the absolute value of the currenttolerance that T-Spice uses, so that low-current and subthreshold behavior can besimulated accurately. The results are quite accurate when T-Spice uses internaltables (its default simulation technique) to represent the model. More accuracycan be achieved by defining a larger gridsize (finer resolution — for example,.gridsize mos 500 500 500 ), or by using direct model evaluation (with the.options deftables=0 command), but this is not necessary in most cases.

Output

The output is a logarithmic plot of the drain current against the gate voltage. Thelogarithm of the current is a straight line for low gate voltages and shows asmooth transition between low-current exponential behavior and high-currentquadratic behavior.



c:\tspro\tutorial\trangm.out

1.51.41.31.21.11.00.90.80.70.60.5

1.0E-6

1.0E-7

1.0E-8

1.0E-9

1.0E-10

vgate (V)

Cur

rent

(A

)id(mn5),0

Circuit Analysis Tutorial Example 12: MOS Transconductance Amplifier


Example 12: MOS Transconductance Amplifier

The basic transconductance amplifier produces an output current proportional inmagnitude to the difference between the input voltages. Proper modeling of thetransconductance amplifier’s output current behavior, over a broad range ofdifferential voltages, requires accurate subthreshold modeling of its transistors.Otherwise, the predicted trasnconductance characteristics will be inaccurate. Thiscircuit can be simulated correctly in subthreshold by T-Spice.

Schematic transamp.sdb

Input transamp.sp

Output transamp.out



Schematic



Input

.include ml5_20.mdmn1 vn1 vbias GND GND nmos l=10u w=6umn2 vm1 in1 vn1 GND nmos l=6u w=6umn3 out in2 vn1 GND nmos l=6u w=6ump1 vm1 vm1 Vdd Vdd pmos l=6u w=6ump2 out vm1 Vdd Vdd pmos l=6u w=6uvin1 in1 GND 2Vdd Vdd GND 5.0vbias vbias GND 0.7vdiff in2 in1 0.0vout out GND 2.5.options abstol=1E-14.dc vdiff -1 1 0.01.print dc i1(vout)

This circuit is identical to the one described in Example 4, except that the outputstage (inverter) has been removed, and a voltage source has been connected tothe output so that the transconductance characteristics of the amplifier can bemeasured.

The .options abstol command changes the absolute value of the currenttolerance that T-Spice uses, so that low-current and subthreshold behavior can besimulated accurately.



Output

c:\tspro\tutorial\transamp.out

1 00 50 0-0 5-1 0

2

1

0

-1

-2

Cur

rent

(nA

)i1(vout),0

1 00 50 0-0 5-1 0

2

1

0

-1

-2

Cur

rent

(nA

)

id(mn3),0

1.00.50.0-0.5-1.0

2

1

0

-1

-2

vdiff (V)

Cur

rent

(nA

)

id(mn2),0

Circuit Analysis Tutorial Design Examples


Design Examples

Following are design examples created and simulated by T-Spice Pro. Use S-Editto run all of the examples.

Wide-Band GaAs IC Amplifier

This example describes the design and performance of a wide-band GaAs ICamplifier. The amplifier consists of two cascaded stages. It features ahigh-voltage gain (>20 dB), wide bandwidth, and very low input VSWR. Thisamplifier is useful for many signal processing and instrument/measurementapplications.

The example consists of four sub-examples for characterizing the AC, DC andtransient performance and measuring S-parameters of the circuit. The examplefiles are in the ~\example\gaasamp directory. The contents of the directory are:

gaas.mdGaAs MESFET and diode model parameters for the example.

amp_ac.sdb The amplifier schematic, containing commands for AC, noise, and small-signal parameter analysis.

amp_dc.sdb The amplifier schematic, containing commands for DC transfer analysis.



AC Analysis Example

; Use File > Open to open amp_ac.sdb .

; Use Module > Open to open module amp_ac (the top module) if it is not alreadyopen.

; Follow the procedures described in the Waveform Probing Tutorial on page 95 toexport, simulate and probe the design.

; To probe into a subcircuit, select the subcircuit and use the Probe toolbar buttonsto move through different levels. Click the Probe Push button to get into thenext lower level of the circuit, the Probe Pop button to go back to the next higherlevel, and the Probe Top Level button to go to the top level.

Use the analysis buttons on the Probe toolbar to view the results of differenttypes of analyses.

; Select the AC/Noise button and click on nodes to view AC analysis results. Clickon devices to view noise analysis results.

amp_spar.sdb The amplifier schematic, containing commands for analyzing the scattering parameters of the circuit.

amp_tran.sdb The amplifier schematic, containing commands for transient analysis.



; Select the Operating Point/Small Signal button and click on nodes to view DCoperating point values. Click on devices for small signal parameters.

The measurement results are listed in the output file amp_ac.out .

DC Analysis Example

; Use File > Open to open amp_dc.sdb .

; Use Module > Open to open module amp_dc (the top module) if it is not alreadyopen.

; Follow the procedures described in the Waveform Probing Tutorial on page 95 toexport, simulate, and probe the design.

; Select the DC Transfer button in the Probe toolbar. Click on nodes to view DCtransfer analysis results.

; Select the Operating Point/Small Signal button and click on nodes to view DCoperating point values. Click on devices for small signal parameters.

Transient Analysis Example

This example contains a polynomial voltage controlled voltage source. Thisprovides a ramp-up sinusoidal wave as an input source.



; Use File > Open to open amp_tran.sdb .

; Use Module > Open to open module amp_tran (the top module) if it is notalready open.


Use the analysis buttons on the Probe toolbar to view the results of differenttypes of analyses.

; Select the Transient button and click on nodes to view transient analysis results.Click on devices to view noise analysis results.

; Select the Operating Point/Small Signal button. Click on nodes to view DCoperating point values. Click on devices for small signal parameters.

S-parameter measurement example

; Use File > Open to open amp_spar.sdb .

; Use Module > Open to open module amp_spar (the top module) if it is notalready open.



The circuit is wired in the same way that s-parameters are measured. The moduleamp in the circuit is the amplifier that was studied in the previous threeexamples.


; Click on ports S11, S21, S12, and S22 to find the s-parameters S11, S21, S12, andS22 of the amplifier.

Voltage Controlled Ring Oscillator

This example describes the design and performance of a voltage-controlled ringoscillator. The ring VCO consists of a control stage that provides bias and tuningvoltage and seven differential cells that form a ring oscillator. The tuning voltagefrom the control stage controls the frequency of the ring oscillator. Theapplications of VCO include frequency modulators, tone generators, A/Dconverters, and digital voltmeters.

The example files are in the ~\example\ringvco directory. The contents of thedirectory are:

mosis2u.md MOSIS MOSFET 2um model parameters. This is the model that is used in simulating the design.



; Use File > Open to open ringvco.sdb .

; Use Module > Open to open module ringvco (the top module) if it is not alreadyopen.


ringvco.sdb The ring oscillator schematic, containing commands for transient analysis.

tech.sdb A small library of technology setup modules which can be included in S-Edit schematics. Some of these modules are used in the above design.

vco.c An external T-Spice macromodel of a voltage-controlled oscillator.

vco.dll A DLL which contains the VCO macromodel described above. This DLL is used by T-Spice during simulation.

vcomacro.sp A Spice file showing the performance of the VCO macro-model. This file has macromodel parameters that were tuned to match the performance of the actual circuit in ringvco.sdb.



This example will be modeled using the user-defined external model feature inT-Spice. The file vco.c is the ring VCO model written in the C programminglanguage. You can compile and build the file into a dynamically linked library,vco.dll , before you simulate the circuit. You can then include vco.dll in theSPICE file for simulation in T-Spice.

; Use File > Open to open vcomacro.sp . This file includes the file vco.dll .

; Select Simulation > Run Simulation to simulate the file.

Note: For more information on the external model feature in T-Spice, see User-DefinedExternal Models on page 634 of the T-Spice User Guide and Reference.

8-Bit Analog-to-Digital Converter

The design used in this example is an 8-bit analog-to-digital converter (ADC).The converter digitizes music signals with a frequency range of 20Hz–20kHz.Due to the limitations of practical anti-aliasing filters, the sampling rate is set tobe 83 kHz, about twice the Nyquist rate. The A/D conversion time is 12ms. Inorder to archive 8-bit accuracy, the quantization error should be less than 0.01V.

The example file is in the ~\example\adc directory.

; Use File > Open to open adc8.sdb .



; Use Module > Open to open module adc_sp (the top module) if it is not alreadyopen.


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