Digital Design with SM Charts : : 2004.01.09

ContentsSM Charts properties

Derivation of SM Charts

Implementation of the Dice game

Alternative realizations for SM Charts using Microprogramming

Linked State Machine

SM Charts propertiesASM (Algorithmic State Machine)Often used to design control units for digital systemsUseful in the H/W design of digital systemsEasier to understand the operation Leads directly to a hardware realization

Components of SM chart(c) Conditional Output boxConditionalOutput list

Example of an SM chart

S1/Z1Z2X1Z3 Z4X3X2Z5One entrance pathOne state010112013nLinkPath aLinkPath bn exit pathsSMblock

Equivalent SM BlocksX1Z2X2S1/Z1S2/S3/(a)1100X2Z2X1S1/Z1S2/S3/(b)1100Z2X10Z2=1 if X1=0S2 if X2=0S3 if X2=1Z2=1 if X1=0S2 if X2=0S3 if X2=1

Equivalent SM Charts for a combinational NetworkA+BCS0/(a)10Z1S0/ACBZ1111000(b)Z1=A+A`BC=A+BC

SM Block with feedbackS0/xS0/x10(a) Incorrect(b) CorrectEvery valid combination of input variables must have exactly one exit path defined

No internal feedback within an SM block is allowed01

Conversion of a state Graph to an SM chartSo/ZaS1/ZbS2/Zc1/00/00/01/01/Z20/Z1S0/ZaxS1/Zbx(a) State graphS2/ZcxZ1Z2000111011100Link 1Link 2Link 3(b) Equivalent SM chart

Derivation of SM ChartsFirst, draw a block diagram of the system we are controlling

Next, define the required input and output signals to the control network

Then, construct an SM char that tests the input signals and generates the proper sequence of output signals

EX1.SM Chart for Binary MultiplierS0/StS1/MShAd0110LoadKS2/ShKS3/Done0011St : start, M : LSB, Ad : add,Sh : shift, K : last shift

Entity Mult isport(CLK,St,K,M: in bit;Load,Sh,Ad,Done: out bit);End Mult;Architecture SMbehave of Mult issignal State, Nextstate : integer range 0 to 3;begin process(St, K, M, State)begin Load

The player wins if the sum is 7 or 11The player loses if the sum is 2,3,12otherwise, the sum is referred to as a point and roll again

The second or subsequent, the player wins if the sum equals the pointthe player loses if the sum is 7, Otherwise, the player roll again until player wins or losesEX2.Dice GameRule

EX2.Dice GameDisplay1-to-6CounterAdderDisplay1-to-6CounterPointRegisterComparator

TestLogic

Control

WinLoseRbResetRollDiceGame ModuleD7SpEqD2312D711Sum

Flowchart for Dice GameRoll diceSum = 7 or 11Sum = 2,3,12Sum = PointSum = 7ResetResetRoll diceLoseWinStore sum inPoint registerYYYYYYNNNNNN

S0 /RbS1 /RbD711D2312SpS3/LoseResetS4 /RbS5 /RbEqD7S2 / WinResetRollRoll00000000011111111110 SM chart for Dice GamePress and ReleaseS0 : No buttonS1 : Button PressedS2 : WinS3 : Lose S4 : No button S5 : Button Pressed

Entity DiceGame isport (Rb, Reset, CLK: in bit; Sum: in integer range 2 to 12; Roll, Win, Lose: out bit);End DiceGame;

Library BITLIB;Use BITLIB.bit_pack.all;

Architecture DiceBehave of DiceGame issignal State, Nextstate: integer range 0 to 5signal Point: integer range 2 to 12;signal Sp: bit;beginprocess(Rb, Reset, Sum, State)beginSp

when 2 => Win

Entity Game is port(Rb, Reset,Clk : in bit; Win, Lose: out bit);end Game;

Architecture Play of Game is component Counter port(Clk, Roll : in bit; Sum : out integer range 2 to 12); end component;

Complete Dice Gamecomponent Dicegame port(Rb, Reset,Clk : in bit; Sum : out integer range 2 to 12; Roll, Win, Lose : out bit); end component;signal roll1 : bit; signal sum1: integer range 2 to 12; begin Dice:Dicegame port map(Rb,Reset,Clk,sum1,roll1,Win,Lose); Counter port map(Clk,roll1,sum1); end Play1;

Implementation of Dice game

PLA

RbResetD711D7D2312EqCBAWinLoseRollSpA+B+C+Clock

PLA Table for Dice Game

A+ = ABCRbD711D2312+AC+ARb+AD7Eq,

B+ = ABCRb(D711+D2312)+Breset+ACRb(Eq+D7)

C+ = BRb+ABCD711D2312+BCReset+ACD7Eq,

Win = BC, Lose = BC, Roll = BCRb

Sp = ABCRbD711D2312Maps Derived from the previous table

architecture Dice_Eq of DiceGame issignal Sp, Eq, D7, D711, D2312 : bit : =0;signal DA, DB, DC, A, B, C, : bit : =0;signal Point : integer range 2 to 12 ;beginprocess(CLK)beginif rising_edge(CLK) then A

Win

MUX1Inputs MUX2Register

Alternative realizations for SM Charts using Microprogramming The only input to PLA come from state register Test controls MUX1 with inputs NSF or NST decided by inputs BOOLEAN (NST: Next State True) Must have only Moore outputs (Outputs depend on only current state)

Linked State MachineA sequential machine becomes large and complex,Desirable to divide the machine into several smaller machines linked together.Each of the smaller machines is easier to design and implement.SOMESTATESSA / ZAZBOTHERSTATES01Machine A(calling machine)IDLEZAOTHERSTATES01Machine B(called machine)SB/ ZB