week4_u

EECS 270C / Winter 2014 Prof. M. Green / U.C. Irvine 1

Advantages of Using CMOS

Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized Mechanically robust Lends itself very well to high integration levels Analog CMOS process usually includes non-salicided poly layer for

linear resistors.

SiGe BiCMOS is very useful but is a generation behind currently available standard CMOS


fT is the frequency at which becomes 1.

idi g

=gm

2fCgs

gm = CoxWL

VGS Vt( )

Cgs = WLCox

fT gives a fundamental speed measure of a technology.

0.25 m CMOS: fT ~ 23GHz (VDD = 2.5V) 0.18 m CMOS: fT ~ 57GHz (VDD = 1.8V)

T = 2fT =

L2VGS Vt( )

VDD

Cgs

VGS

vgs

ig id

Transistor fT Calculation


Static CMOS propagation delay:

fall CL

nWnLn

VDD Vt( )

rise CL

pWpLp

VDD Vt( )

Assume: Wp = 3Wn for optimum noise margin. Lp = Ln = Lmin

rise = fall =Lmin (Wp +Wn )Cox

nCoxWnLmin

(VDD Vt )

=Lmin

2

n1+

WpWn

#

$ % %

&

' ( (

1VDD Vt

=4T

Operation is 4X slower than theoretical maximum due to n-channel & p-channel gates connected in parallel.

(Actual values will be higher due to high diffusion capacitances present in sub-micron transistors.)

Vin Vout

WnLn

WnLn

WpLp

WpLp


IG

ID

fT = 57GHz

Vout Vin

= 18ps 6.4T

n-channel ac simulation to determine fT: CMOS inverter transient simulation:

Verifying with simulation:


Single-Ended Signaling in CMOS

Series R & L cause supply/ground bounce. Resulting modulation of transistor Vts result in pattern-dependent jitter.

Vin Vout

sub

IDD

ISS

VDD

VSS

Vin

Vout

ISS

IDD


Rs = 0 Ls = 0

clock out

Rs = 5 Ls = 5nH

clock out

data in clock in clock out data out

" V DD

" V SS

" V DD

" V SS

data out

Rs = 5 Ls = 5nH

Effect of Supply/Ground Bounce on Jitter


Summary of CMOS Gate Performance

1. Simple & straightforward design. 2. Robust operation. 3. Nearly zero static power dissipation.

Advantages of static CMOS gates:

1. Full speed of transistors not exploited due to n-channel & p-channel gate in parallel at load.

2. Single-ended operation causes current spikes leading to VDD/VSS bounce.

3. Single-ended operation also highly sensitive to VDD/VSS bounce leading to jitter.

Disdvantages of static CMOS gates:


Current-Mode Logic (CML)

Based on conventional differential pair

Differential operation

Inherent common-mode rejection

Very robust in the presence of common- mode disturbances (e.g., VDD / VSS bounce)

CML inverter: VDD

Vin+ Vin-

Vout- Vout+

ISS

R R

CL CL


Vin(DC ) =Vout (DC ) =VDD 12

ISSR

To keep current source transistor in saturation:

VS >VBIAS Vt

VS =Vin(DC ) VGS

Vin(DC ) >VBIAS + VGS Vt( )

12

ISSR+

_

12

ISSR+

_

VDD

R R

WL

WL

ISS

VIN(DC )

VOUT(DC )

VOUT(DC )

VS VGS

+ _ VGS

+ _

VBIAS

DC Biasing of CML Inverter

VIN(DC )


Vhigh =VDDVlow =VDD ISSR

Vswing = ISSR

To achieve full current switching:

Vswing VGS Vt( )|ID=ISS =2ISS

nCoxWL

Vmin

VswingVmin

> 1 for correct operation

VswingVmin

= R 12

CoxWL

ISS

Logic Swing & Gain of CML Inverter

VDD

VDD VDD-ISSR

ISS

R R

CL CL

WL

WL

VDD-ISSR VDD

ISS 0


Av = gmR = R CoxWL ISS

Small-signal voltage gain:

Note: rising & falling time constants are the same

Recall

VswingVmin

= R 12

CoxWL

ISS > 1

for full switching

VswingVmin

=Av2

Av 2

(Assuming fanout of 1)

rise/fall time constant:

= RCL

CL = CoxWL

= R(WLCox )

Small-Signal Behavior of CML Inverter


Speed vs. Gain in Logic Circuits

Largest possible gain-bandwidth product is desirable.

fast input transition: step response determined by

slow input transition: step response determined by Av


Av = R nCoxWL ISS

Av2 = nCox

WL

ISSR2

=nL2

RWLCox( ) ISSR( )

Av2 =

nL2

Vswing

large-signal gain-bandwidth product

Av2

=

nL2

Vswing

Relationship between Av , , and Vswing

Larger logic swing preferred for higher gain-bandwidth product

Larger Vswing Larger Vmin smaller W/L larger current density

Vswing


Suppose we decrease current density by increasing W/L:

WL2 Vmin

12

, CL 2

R 12

= RC 2Slower!

Thought Experiment

R R

WL

WL

R R

WL

WL

ISS ISS


Note that the load is only one gate capacitance:

CML speed ~ 2.5 times faster than static CMOS

IG

ID

fT = 57GHz

n-channel ac simulation to determine fT:

CML buffer transient simulation:

= RCL = RgmT

=AvT

2

T

= 8ps 2.9T


Typical Vswing: Should be large enough to allow sufficient gain-bandwidth product. Should be small enough to prevent transistors from going into triode. * CML will still work in triode (unlike BJT), but there is no additional speed benefit.

Vswing = ISSR

Once Vswing has been chosen, designer can trade off between gain & bandwidth by parameterizing between R & ISS:

Higher speed: ISS R

Higher gain: ISS R

Av = R CoxWL ISS

= R(WLCox )

0.3 VDD


Other Benefits of CML Gates

1. Constant current bias VDD / VSS bounce greatly reduced

KCL sets this current to be nearly constant.

ISS

ISS


data in clock in

Rs = 0 Ls = 0

clock out

clock out

Rs = 5 Ls = 5nH

clock out

data out

" V DD

" V SS

" V DD

" V SS

data out

Rs = 5 Ls = 5nH


2. Non-inverting buffer available without additional delay: CMOS:

inverter buffer

CML:

inverter buffer

Vin+

Vin

Vout+

Vout

Vin+

Vin

Vout

Vout+

tp 2tp


Fanout & Scaling of CML Gates

1x

=

nx

= All voltages unchanged from unit-sized buffer. Currents & power increase by factor of n.

ISS

Vin+ Vin-

Vout- Vout+ R R

WL

WL

nISS

Vin+ Vin-

Vout- Vout+ R/n R/n

n WL

n WL


For fanout of n:

= nCLR

Av2

=

2nL2

Vswing

increases linearly with fanout.


From interconnect, etc.; assumed not to scale with buffer sizes

= nCL +Cp( ) R / n( ) = WLCoxR 1+CpnCL

%

& ' '

(

) * *

Av2 = 2nCox

nWL nISS( ) R / n( )

2= 2nCox

WL ISSR

2

Av2

=

2nL2

Vswing 1+CpnCL

%

& ' '

(

) * *

1

Should set

n 0.1 Cp /CL( )degradation due to interconnect capacitance

to minimize

Power (proportional to n) determined primarily by interconnect capacitance!


Sub-micron MOSFETs obey square-law characteristics only in a limited region!

CML buffer design procedure:

1. Determine largest allowable ISS (usually limited by electromigration constraints) 2. Choose unit-sized n-channel transistor (typically W/L=20) 3. Run a series of simulations to determine optimum value of R:

R too small: full current switching not achieved R too large: slower than necessary

4. Choose minimum scaling factor after laying out some test buffers of various sizes and determining approximate value of interconnect capacitance Cp.

VGS

ID

Mobility reduction (linear)

Square-law behavior

Weak inversion (exponential)

+ _ VGS

ID


1. Determine largest allowable ISS

I D Imax

standard layout shared drain (1/2 diffusion capacitance)

Imax independent of W determined by electromigration limits


R = 1200 ISSR = 480mV

tp = 12ps *R optimum*

R = 900 ISSR = 360mV

tp = 10ps R too small

R = 1500 ISSR = 600mV

tp = 14ps R too large

CML Design Procedure Example

ISS = 400A

WL

=4 m

0.18 m

Choose:


Parameterizing Between Gain & Bandwidth ISS = 100 A R = 4.8 k Av = 9.3 dB BW = 2.6 GHz

ISS = 200 A R = 2.4 k Av = 7.1 dB BW = 5.5 GHz

ISS = 400 A R = 1.2 k Av = 3.9 dB BW = 11.5 GHz


R GBWGSCALE MSCALE

ISS GSCALE MSCALE

GBW

WL GSCALE MSCALE

GSCALE: Global scaling parameter (depends on Cp) MSCALE: Local scaling parameter (depends on fanout or bit rate) GBW: Gain-bandwidth parameter

Parameterized CML Buffer


CML with p-channel Active Load

p-channel load transistors operates in triode region: Increased capacitance and mismatch result

Can be used if linear resistors are not available.


Capacitance Comparison (1)

Poly resistor:

p-channel MOSFET:

C 12Cpolysub

C Cdepletion +12 Cchannelgate + Cchannelsub( )

gate

sub

channel


Cpoly-sub Cchannel-sub : 0.13 fF/m2 Cdepletion : 1.20 fF/m2

Cchannel-gate : 7.80 fF/m2

Poly resistor:

p-channel MOSFET:

C 12Cpolysub

C Cdepletion +12 Cchannelgate + Cchannelsub( )

Wchannel = Wdiff = 2.5 m Lchannel = 0.18 m

Ldiff = 0.3 m

Wpoly = 0.6 Lpoly = 2.5

= 0.1 fF

= 0.9 fF + 1.8 fF + .03 fF = 2.8 fF


(Numbers based on TSMC 180nm CMOS process)


R = 1.2 k s = 235 /! Wr = 0.6 m Lr = 2.5 m Cres = 0.1 fF

Wp = 2.5 m Ldiff = 0.3 m

Cd2 = 2.8 fF

M2 M2

M1 M1 M1 M1

Cd1 = 3.7 fF Cg1 = 5.8 fF



Pulse Response Comparison PWin = 100ps

resistor load R = 1.2 k

td = 16 ps; PWout = 100 ps

p-channel load (W/L)p = 2.5 m / 0.18 m td = 20 ps; PWout = 98 ps


Eye Diagram Comparison including mismatch effects

resistor load

= 1.5% mismatch

RR

160mV gate-referred mismatch

IDID

= 4% mismatch

p-channel load

ISI

DCD


MA MA

MB MB

MA MA

Series-Gated CML Topology

XOR gate:

Common-mode voltage of BP/N critical:

Too low current source transistor biased in triode Too high Transistors MB biased in triode


VBP VBN

VS

I1 I2

I1 I2

-ISS

ISS

Slope = gm

Transistors should be biased in saturation to realize maximum gm . Especially important when gate voltages exhibit slow slew rates

BP BN

VBP VBN

Series-Gated CML (2)


VB(cm) = 1.6

VB(cm) = 1.3 VB(cm) = 1.0

VBP VBN

t

VB(cm) = 1.6

VB(cm) = 1.3 VB(cm) = 1.0

DC current:

Transient response: (400mV amplitude sine wave applied to BP/BN)

IBP IBN

IBP IBN


Level-Shifting CML Buffer

VDD

Rcm

ISS

R R

+

_

ISSRcm

Output levels:

Vhigh = VDD ISSRcm( )

Vlow = VDD ISSRcm( ) ISSR

Used to drive clock inputs of series-gated CML gates

Vswing = ISSR

DC levels shifted down by ISSRcm Vswing unchanged


Be reassigning the inputs, the XOR can be transformed into a Select circuit. Used in a 2:1 multiplexer.

CML Select Circuit

ISS

R R

AP AN BP BN

SELA SELB

OUTP OUTN

SELA

AP/N

BP/N

OUTP/N


CML Latch

By setting BP/N = OUTP/N, we can construct a CML latch:

ISS

DP DN

OUTP OUTN

CKP CKN


CML D Flip-Flop

Output OUTP/N is synchronized with CKP/N falling edge.

DP DN

CKP CKN

XN XP

XP XN

OUTN OUTP

CKP CKN

CKP/N

DP/N

OUTP/N


CML Latch Design Considerations

IGG

VGG

dc operating points

Necessary criterion for bistability:

rgg =2

1/ R gm=

2R1gmR

< 0 at middle operating point

(Equivalent to loop gain = gmR > 1)

slope=1/rgg

IGG VGG

12

ISS

R R


gmR > 1

gmR 1

gmR 1

transparent latch

Avoiding Latch Transparency

XP/N


R=1000

R=800

R=600

GBW parameter can be increased to ensure bistability.

gmR > 1

gmR 1

gmR < 1

DP DN

CKP CKN

QINQIP

QIP QIN

OUTNOUTP

CKPCKN

XP XN

XP XN


Buffering Clock Signals (1)

Clock signals (generated from VCO or clock divider) often drive large capacitive loads.

1x

Fanout = n

= nRC f3dB =1

2

C

C

C

For a large fanout, attenuation of clock amplitude will occur.

1x

1x

n


1x k x k2 x

n x

m stages

Now is increased by k


Since clock signal is made up of a single frequency (+ harmonics), resonance can be used to increase gain with greatly reduced power dissipation.

Y = 1R

+ jC + 1jL

=(12LC) + j(L / R)

jL

Resonant frequency:

r =1LC

Y = 1R

at resonance

If lossless inductors were available, we could achieve high gain at any frequency simply by choosing the correct inductor value.

Buffering Clock Signals (3)


On-Chip Passive Elements

R = tw

Resistor:

C w d

Capacitor:

d w

substrate

(+ fringing)

Inductor:

t

t w

l

w

Inductance calculation much more complicated!

l

l

l

l

L 0.2 ln 2

t + w

#

$ %

&

' ( + 0.50049+

t + w3

)

* +

,

- . pH/m l

l l


t w

Special case of Greenhouse result

Note for l >> w, L is a weak function of w

To increase effective inductance per unit length, we make use of mutual inductance via spiral structure:

L 0.2 ln 2

t + w

#

$ %

&

' ( + 0.50049+

t + w3

)

* +

,

- . pH/m l

l l

l


Modeling of Spiral Inductor

Design of inductor requires: inductor simulation package (e.g., asitic) trial and error conversion to lumped

element model

number of turns n = 2

1

2

Accurate lumped model should include: Series inductance (self + mutual) & resistance Skin effect (frequency dependent series resistance) Interwinding capacitance Capacitance to substrate Substrate capacitance & loss

Procedure for constructing lumped model: 1. 2-port s-parameters over frequency range of interest

(this comes from the inductor simulator) 2. Choose lumped circuit topology. 3. Run simulations to find the optimal lumped circuit

element values such that the the circuit s-parameters are sufficiently close to the inductors s-parameters (can use .net and .optimize in HSPICE)


Parameters most relevant to circuit designers: Inductance Series resistance Self-resonant frequency

http://rfic.eecs.berkeley.edu/~niknejad/asitic.html

Link to asitic web pages:

Modeling of Spiral Inductor (cont.)

Inductor magnitude impedance vs. frequency


1

2

Cint

L Rs

Cox2 Cox1

Csub1 Csub2 Rsub1 Rsub2

1 2

L: Rs:

Cint: Cox:

Csub/Rsub:

Self/mutual inductance Series resistance Interwinding capacitance Oxide capacitance Substrate capacitance/resistance

Values of L and Rs in lumped model should correlate with physical parameters. Values of other lumped model elements need not necessarily correlate with physical parameters.

Modeling of Spiral Inductor (cont.)


Parasitic capacitances usually combine with load capacitance L should be decreased slightly

Series Rs has more important effect:

Y = 1R

+ jC + 1Rs + jL

L

Rs

C R

" Y = 1" R

+ jC + 1j " L

R C L'

At resonance, Im [Y(jr)] = 0:

r2

=1

LC

RsL

$

% &

'

( )

2

r2

=1# L C

Y jr( ) = 1R +CRs

L

" Y jr( ) = 1" R

" L = L

1 CRs2

L

" R = R || LCRs

#

$ %

&

' (

Slight increase in effective inductance Very important effect!


Differential-mode ground Sets common-mode output voltage

Gain at resonant frequency = gm R CL resonates out with L

CML Tuned Amplifiers (1)


Symmetric inductor structure can be used:

Single structure allows more inductance to be realized from mutual coupling less series resistance



Gain is much higher at resonance, but depends completely on Rs. Variation in gain correlates with variation in metal (not resistor) sheet resistance.


Higher-gain topology:


R C L Vswing

+

_

Iin

IL

Let Vswing = 500mV, L=0.5nH, f =10GHz:

Spiral inductor should be wide enough to meet ac electromigration specs.

Iin =Vswing

" R

IL =Vswing # L

IL = 16mA

Watch out for ac current amplitude in inductors!



Inductors in Broadband Circuits

R

R

Vin Vout

+

_

LC lossless transmission line (Z0) R

RCVin

Vout

+

H(s) = 12

1

1+ s CR2

| H( j) |

H( j)

90!

2CR

H(s) = 12esTd

Td = LC

for R = Z0

| H( j) |

H( j)

0.5 0.5

slope = -Td


Series Peaking (1)

Cd Cg

Cd Cg

Lser

With direct connection of 2 buffers, output & input capacitances are in parallel:

By connecting an inductor between the capacitors, the bandwidth and delay increase:

Series peaking


Series Peaking (2)

Cd = Cg = 16 fF R = 400

Lser Cd Cg

R

Vin+ Vin-

Vx+

Vx-

R LserCd

Using

Lser CdR2set

VxVin

VxVin

#

$ %

&

' (

Lser = 0 BW = 6.3 GHz

Lser = 3.5 nH BW = 8.3 GHz

Lser = 3.5 nH

Lser = 0

Frequency response:

Vin

Vx (Lser = 0)

Transient response: Vx (Lser = 3.5 nH)

Vin

Vx (Lser = 0)

Series peaking provides speed at the expense of extra delay.


Shunt-Peaking (1)

By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance.


Properties of Shunt-Peaking

r2

=1

LCL1 CLR

2

L

$

% &

'

( )

Resonant frequency:

No resonance for

LCLR

2< 1

CL

X Re s

Im s

L = 0: pole at s = 1/RC

X O

L 0: zero at s = R/L additional pole at s (1/CR + R/L)

Z(s) = R 1+ s L

R1+ sCLR + s

2LCL

Z( j) = R 1+ j L

R12LCL( ) + jCLR

Frequency response:


L = 0BW = 6.3 GHz

LCLR

2= 0.3

L = 1.8 nH BW = 9.4 GHz

LCLR

2= 0.6

L = 3.7 nH BW = 14.3 GHz

Shunt-Peaking -- AC Response

Use of shunt-peaking increases small-signal bandwidth

CL = 38 fFR = 400


Shunt Peaking Transient Response

Step Response:

L = 0td = 13.4 ps

L = 1.8 nH td = 8.5 ps

L = 3.7 nH td = 6.7 ps

Pulse Response (tin = 50 ps):

L = 3.7 nH tout = 50.8 ps ISI = 16 mUI

L = 1.8 nH tout = 50.0 ps ISI = 0 mUI

L = 0 tout = 48.7 ps ISI = 26 mUI


LCLR

2= 0

LCLR

2= 0.3

LCLR

2= 0.6

Shunt Peaking ISI vs. Pulse Width

ISI (UI)

Input pulse width


Other Advantages of Shunt-Peaking

CML load is passive & linear

Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance inductors can be placed far away from other CML circuit elements.


long metal lines

Effect of Shunt-Peaking Inductor Parasitics (1)

Series resistance RP simply adds to R Shunt capacitance CP resonates with L

L L

R R

CL CL CL CL

L L

R R

RP RP

CP CP


LCLR

2= 0

LCLR

2= 0.3

LCLR

2= 0.6

LCLR

2= 0

LCLR

2= 0.3

LCLR

2= 0.6

Moderate amount of parasitic capacitance has similar effect to slightly larger inductor.

Disadvantages of using passive inductors: Consume huge die area Difficult to design & model

Effect of Shunt-Peaking Inductor Parasitics (2)

CP = 0

CP = 0.2CL

Input pulse width

Input pulse width

ISI (UI)

ISI (UI)


Multi-layer Inductors (1)

metal 6

metal 5 d

Distance d between two metal layers is much smaller than lateral distances (e.g., w, l, s)

metal 6

metal 5

d


12

#

$ %

&

' ( =

L1 MM L2

)

* +

,

- .

i1i2

#

$ %

&

' (

L1 L2 1 2

+

_

+

_

i1 i2

2-port representation of coupled inductors:

M = k L1L2

Passivity constraint: 1k

For metal geometries close to each other, k is close to unity.

series connection of coupled inductors:

L1 L2

i1

i2

M 1

+

_ 2

+

_

series =1 +2 = (L1 + M)i1 + (L2 + M)i2

iseries = i1 = i 2

Lseries =seriesiseries

= L1 + L2 + 2M

For L1 = L2 = L, we have:

Lseries = 2L + 2M = 2L(1+ k) 4LIn general, for n layers we have:

Lseries n2L

Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance.



Ci

Cj

For more details, see: A. Zolfaghari, A. Chan & B. Razavi, Stacked inductors and transformers in CMOS technology, IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620-628.

Leffective 4L

Ceffective 13

Ci +1

12Cj

Effective Capacitance:



metal 6 only 100 x 100 w = 4; s = 2; n = 4 L=2.0 nH R=6.9

metal 6 over metal 4 46 x 46 w = 4; s = 2; n = 2.5 L=2.0 nH R=12.5

+


Area comparison:


Active Inductors (1)

Rgyr

+

_ v1

i1 +

_

v2

i2

Ideal gyrator:

v2 = Rgyr i1v1 = Rgyr i2

Impedance inversion:

Rgyr

+

_ vin

iin

C

Zin = Rgyr2 sC( )

Port 1 exhibits inductance when port 2 is connected to a capacitance.

v1v2

"

# $

%

& ' =

0 RgyrRgyr 0)

* +

,

- .

i1i2

"

# $

%

& '

Matrix representation (Z-parameters):



RG

+

_

v1 i1

+

_ v2

i2

i1 applied with port 2 open-circuited:

i2 applied with port 1 open-circuited:

v2 =1

gmi1

v1 = RG 1

gm

#

$ %

&

' ( i2

(Assume RG gm > 1)

v1v2

"

# $

%

& ' =

1 gm RG 1 gm( )1 gm 1 gm

)

* + +

,

- . .

i1i2

"

# $

%

& '

Complete Z-parameters (lossy/active gyrator):

Consider common-drain configuration:


v1v2

"

# $

%

& ' =

1 gm 1 gm RG1 gm 1 gm)

* +

,

- .

i1i2

"

# $

%

& '

+

_

vin


Interpretation of non-ideal matrix entries:


Zsource =1

gm

1+ sCgsRG1+ sCgs gm"

# $

%

& '

At low frequencies (Cgs open) Zsource = 1/gm

At high frequencies (Cgs short) Zsource = RG


Impedance at port 1 with port 2 terminated with transistor Cgs:


gmCgs

1CgsRG

1gm

RG

Zsource

Leff CgsRG

gm=

RGT

gmRG > 1

Equivalent circuit:

+

_

vin

1gm

RG 1

gm

Cgs RGgm



Av =gm 1gm 2

=W1W2

For shunt peaking:

L 0.3CLR2

CgsRGgm2

= 0.3 CLgm2

2

gm 2RG = 0.3CLCgs

Low-frequency gain:

CML Buffer with Active Inductor Load

WL

"

# $

%

& ' 1

=40.18

WL

"

# $

%

& '

2

=2.50.18

ISS = 400A


Active Inductor AC Response

RG = 4k

RG = 2k

RG = 0


Active Inductor Transient Response (1)

RG = 0 PW = 97ps

RG = 5k PW = 100 ps

RG = 10k PW = 104 ps

Differential signals:


Active Inductor Transient Response (2)

Problem: n-channel load shifts output by Vt. Vsb > 0; body effects exacerbates this effect..

Single-ended input

Single-ended outputs

Single-ended signals:


Alternate topology: p-channel load exhibits lower Vt (Vbs = 0)

Active Inductor Alternate Topology

differential

single-ended

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