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IEEE- International Conference On Advances In Engineering, Science nd Management (ICESM -2012) March 30, 31, 2012 534

Power Reduction in Scan Based BIST Using

BS-LFSR and Scan-Chain Ordering

# Jay Department Of Electronics and Communication Engineering(Applied Electronics),

Vandayar Engineering College,Thanjavr,Tamil nadu, [email protected]

Chitra ME #2Assistant PrfessrEG pillai Engineering cllegeNagapatinam

chirariaharhii@maicm

Abstract- The design for low power has become one of

the greatest challenges in high-performance very large

scale integration (VLSI) design. It has been found that

the power consumed during test mode operation is oen

much higher than during normal mode operation. This

is because most of the consumed power results from the

switching activity in the nodes of the circuit under test

(CUT), BIST technique uses linear feedback shi

register (LFSR) for generating test pattern. The

proposed design, called bit-swapping LFSR (BS-LFSR),

is composed of an LFSR and a multiplexer. Whenused to generate test patterns for scan-based built-in

self-tests, it reduces the number of transitions that

occur at the scan-chain input during scan shi

operation by when compared to those patternsproduced by a conventional LFSR. Hence, it reduces the

overall switching activity in the circuit under test

during test applications. These techniques have a

substantial effect on average- and peak-power

reductions with negligible eect on fault coverage ortest application time.

Built-in self-test (BIST), linear feedback shiregister (LFSR), low-power test, pseudorandom pattern

generator, scan-chain ordering, weighted switching

activity SA).

I.INTRODCTION

The great challenge in high performancevery large scale integration (VLSI) is the design forlow power. There are many tecnique have beenintroduced in terms of power consumption. But all

they focus only on normal mode operation were notkeen on test mode operation[ 1]. Because most of theconsumed power results om the switching activityin the nodes of the circuit under test (CT), which ismuch higher during test mode than during normalmode operation [1]-[3].

There are many technique have beenintroduced for getting low power in test modeoperation [4]-[5]. An important technique to reduce

power consumption is by runing a test at slower

equency than in a normal mode [1]. But it increasestest application time [6]. Then other tecnique is scanchain ordering techniques [7]-[8].

This technique aims to reduce average

power consumption and peak power, but not thecapture power that may result during the test cycle.Then the next tecnique is TPG tecnique for tomodi test vector generated by LFSR to get vector atlower number of transition. But this tecnique only

reduces the average power consumption at the input,but its not reducing at the output. Other techniquesto reduce average-power consumption during scanbased tests include scan segmentation into multiplescan chains [6],[],test-scheduling [12],[13],

tecniques static compaction tecniques and multiplescan chains with many scan enable inputs to activateone scan chain at a time.

There are some new approaches that aim toreduce peak-power consumption during tests,particularly the capture power in the test cycle. Herethe most important tecnique is X lling techniquethat assign values to the dont care of deterministicset of vectors for reducing peak power [15],[16]. The

proposed design, called bit-swapping LFSR (BSLFSR), is composed of an LFSR and a 2 1multiplexer.

Fig.. Block Diagram of Operation.

When used to generate test pattes for scanbased built-in self-tests, it reduces the number oftransitions that occur at the scan-chain input during

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scan shi operation by 50% when compared to thosepattes produced by a conventional LFSR. Hence, itreduces the overall switching activity in the circuitunder test during test applications.

The BS-LFSR is combined with a scanchain-ordering algorithm that orders the cells in away that reduces the average and peak power (scanand capture) in the test cycle or while scaning out a

response to a signature analyzer. The given g.1 iswhole Block Diagram of Operation in that BS-LFSRis combined with a scan-chain-ordering algorithm

that reduces the switching activity in both the testcycle (capture power) and the scanning cycles(scanning power).

II.APPROACH BASED TO DESIGN A BS-LFSR

The proposed BS-LFSR for test-per-scanBISTs is based upon some new observations

conceing the number of transitions produced at theoutput of an LFSR.eon Two cells in an -bit LFSR areconsidered to be adjacent if the output of one cellfeeds the input of the second directly (i.e., without anintervening XOR gate).Lemma Each cell in a maximal-length -stageLFSR (internal or external) will produce a number of

transitions equal to 2 aer going trough asequence of 2 clock cycles.Poo The sequence of s and s that is followed byone bit position of a maximal-length LFSR iscommonly referred to as an sequence. Each bit

within the LFSR will follow the same -sequencewith a one-time-step delay. The -sequencegenerated by an LFSR of length has a periodicit of2 1. It is a well-known standard propert of an sequence of length that the total number of runs ofconsecutive occuences of the same binary digit is2 [3], [17].

Fig.2. Swapping Arrangement for an LFSR.

The begining of each run is marked by atransition between 0 and 1; therefore, the totalnumber of transitions for each stage of the LFSR is2. This lemma can be proved by using the toggle

propert of the XOR gates used in the feedback ofthe LFSR [19].

The bellow diagram is example of the n-stageLFSR. But here in proposed system, Giving a four

number of sequence input which contain a single "1in the input then LFSR produce a random values ofinput continuously. The following Fig.3. is an LFSRwith four inputs.

L L

OFF OFF t3k

Fig.3. Conventional LFSR with four Input

Lemma Consider a maximal-length -stageinteal or exteal LFSR ( > 2). We choose one of

the cells and swap its value with its adjacent cell ifthe current value of a third cell in the LFSR is (or 1)and leave the cells un swapped if the third cell has avalue of 1 (or 0). Fig.2. shows this arrangement foran exteal LFSR (the same is valid for an intealLFSR). In this arrangement, the output of the twocells will have its transition count reduced by

saved = 2(2) transitions. Since the twocells originally produce 2 2 1 transitions, then

the resulting percentage saving is saved% = 25%[19]. In Lemma 2, the total percentage of transitionsavings aer swapping is 25% [18]. In the case wherecell x is not directly liked to cell or cell + 1

trough an XOR gate, each of the cells has the sameshare of savings (i.e., 25%).Lemmas show the special cases where the cell

that drives the selection line is linked to one of theswapped cells trough an XOR gate. In thesecongurations, a single cell can save 50% transitions

that were originally produced by an LFSR cell.Lemma 3 and its proof are given; other lemmas canbe proved in the same way.

Every lemma written for n-stage, but theproposed system is having only a four stage so everylemma will calculate only for four stages. Thefollowing lemma 3 and proof explain that how to ndand reduce the number of transition in the input byswapping of two inputs.Lemma For an exteal 4-bit maximal-lengthLFSR that implements the prime polynomial 4 + x +1 as shown in Fig.4, if the rst two cells d2 and d)have been chosen for swapping and cell do as a

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selection line, then (the output of MX2) willproduce a total transition savings of 4 = 4compared to the number of transitions produced byeach LFSR cell, while has no savings (i.e., thesavings in transitions is concentrated in onemUltiplexer output, which means that will save50% of the original transitions produced by eachLFSR cell).Poo There are eight possible combinations for theinitial state of the cells and . If we thenconsider all possible values of the following state, wehave two possible combinations (not eight, because

the value of in the next state is determined by thevalue of in the present state; also, the value of in

the next state is determined by " xor in thepresent state). Table I shows all possible andsubsequent states.

It is important to note that the overallsavings of 25% is not equally distributed between the

outputs of the multiplexers as in Lemma 2. This isbecause the value of in the present state will affectthe value of and its own value in the next state ((Next) = and (Next) = " xor ). To see theeffect of each cell in transition savings, Table I shows

that 1 will save one transition when moving omstate (0,0,1 to 1,0,0, om 0,1,1 to 1,0,0, om1,0,1 to 0,1,0, or om 1,1,1 to 0,1,0. In thesame time, will increase one transition whenmoving om 0,1,0 to 0,0,0, om 0,1,0 to0,0,1, om 1,0,0 to 1,1,0, or om 1,0,0 to1,1,1. Since 1 increases the transitions in four

possible scenarios and save transitions in other four

scenarios, then it has a neutral overall effect becauseall the scenarios have the same probabilities. For 2,one transition is saved when moving om 0,1,0 to0,0,0, om 0,1,0to 0,0,1, om 0,1,1to 1,0,0,om 1,0,0 to ,1,, om 1,0,0 to 1,1,1, orom 1,0,1 to 0,1,0. At the same time, oneadditional transition is incurred when moving omstate (0,0,1) to (1,0,0) or om (1,1,1) to (0,1,0). Thisgives an overall saving of one transition in four

possible scenarios where the initial states has aprobability of 18 and the nal states of probabilit12; hence, save is given by

save = 1

1

+1

1

+18

1

+1

1 = 14.

()If the LFSR is allowed to move trough a

complete cycle of 4 = 6 states, then Lemma 1shows that the number of transitions expected tooccur in the cell under consideration is 2'. sing

the swapping approach, in 14 of the cases, a savingof one transition will occur, giving a total saving of

14 2 = 2,14. 6 = n=

Dividing one gure by the other, we see that thetotal number of transitions saved at is 50%.

In the special congurations shown inTable II (i.e. Lemmas 310), if the cell that saves50% of the transitions is connected to feed the scanchain input, then it saves 50% of the transitionsinside the scan chain cells, which directly reduces theaverage power and also the peak power that may

result while scanning in a new test vector.

1

Q.-

\

IQ!

LX _tullXr!_-_

D

Fig.4. Exteal LFSR that implements the primepolynomial 4 + x + 1 and the proposed swapping

arrangement. Circuit Diagram of BS-LFSR

TABLE I.POSSIBLE AND SBSEQENT STATES FORCELLS, , AND

(SEE FIG. 4

nNTn\r TR GHE MU 'JL'' L U ' O : N A B C Xl Yl X Y (

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Table III shows that there are 104 LFSRs(inteal and exteal) whose sizes lie in the range of3168 stages that can be congured to satis one ormore of the special cases in Table II to concentrate

the transition savings in one multiplexer output.The following Table II, we know that lemma

om 3-10 have a 50% of power saves in the outputside in both mux. In this proposed system here we

using n=4 so the rst polynomial of LFSR usinglemma 3.x + x + 1. Here we consider the value ofCJ, C and C are d, d and d

TABLE IISPECIAL CASES WHEE ONE CELL SAVES

50% OF THE TNSITIONS.

)W(Il! Q M

J]ymia T y XD U++ : O-' E . C I 0l - xn+':1 b C X n tx"l n x xY'

i +n I _

TABLE IIILFSRS THAT SATISFY ONE OR MOE OF

LEMMAS 310

# t ts J 0 tb - 3,4567 S 1 , 16,9- 21,467930581- ,, 2 .0 14.5, 1} 36 46 7,19 , 5253 - , 8

III. MAIN PROPERTIES OF THE BS-LFSR

There are some important features of theproposed BS-LFSR that make it equivalent to aconventional LFSR. The most important properties of

the BS-LFSR are the following.

The proposed BS-LFSR generates the samenumber of s and s at the output of multiplexersaer swapping of two adjacent cells; hence, the

probabilities of having a 0 or 1 at a certain cell of thescan chain before applying the test vectors are equaHence, the proposed design retains an importantfeature of any random TPG. Furthermore, the outputof the multiplexer depends on tree different cells of

the LFSR, each of which contains pseudo randomvalue. Hence the expected value at the output canalso be considered to be a pseudorandom value.2. If the BS-LFSR is used to generate testpattes for either test per-clock BIST or for theprimary inputs of a scan-based sequential circuit(assuming that they are directly accessible) as shownin Fig, then consider the case that dj will beswapped with d2 and dj and do which is connected to

the selection line of the multiplexers (see Fig.). Inthis case, we have the same exhaustive set of test

vectors as would be generated by the conventionalLFSR, but their order will be different and the overall

transitions in the primary inputs of the CT will bereduced by 50% to 25% [19].

IV. CELL EOEING ALGOITHMThe proposed BS-LFSR can achieve good

results in reducing the consumption of average powerduring test and also in minimizing the peak power

that may result while scanning a new test vector, itcanot reduce the overall peak power because thereare some components that occur while scanning out

the captured response or while applying a test vector

and capturing a response in the test cycle. To solvethese problems, rst, the proposed BS-LFSR hasbeen combined with a cell-ordering algoritmpresented in [8] that reduces the number oftransitions in the scan chain while scaning out thecaptured response.

This will reduce the overall average powerand also the peak power that may arise whilescanning out a captured response. The problem of thecapture power (peak power in the test cycle) will besolved by using a novel algorithm that will reordersome cells in the scan chain in such a way thatminimizes the Hamming distance between the

applied test vector and the captured response in thetest cycle, hence reducing the test cycle peak power(capture power).

In this scan-chain-ordering algorithm, somecells of the ordered scan chain using the algorithm in[8] will be reordered again in order to reduce the

peak power which may result during the test cycle. Iftwo cells are conected with each other, then theprobability that they have the same value at any clockcycle is 0.75.

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Thus, for two connected cells (cells and k),if we apply a sufcient number of test vectors to theCT, then the values of cells and kare similar in75% of the applied vectors. Hence, assume that wehave cell x which is a function of cells y and z If thevalue that cell

xwill have in the captured response is

the same as its value in the applied test vector (i.e.,no transition will happen for this cell in the testcycle) in the majorit of cases where cells y and zhave the same value then we conect cells y and z

together on the scan chain, since they will have thesame value in 75% of the cases. This reduces the

possibility that cell x will undergo a transition in thetest cycle.

The steps in this algorithm are as follows.1. Simulate the CT for the test pattes generated

by the BS-LFSR.2. Identi the group of vectors and responses that

violate the peak power.

3. In these vectors, identi the cells that mostlychange their values in the test cycle and cause

the peak-power violation.4. For each cell found in step (3), identi the cells

that play the key role in the value of this cell inthe test cycle.

5. If it is found that, when two cells have a similarvalue in the applied test vector, the concernedcell will most probably have no transition in the

test cycle, then connect these cells together. If itis found that, when two cells have a differentvalue, the cell under consideration will most

probably have no transitions in the test cycle,

then connect these cells together trough aninverter.

H ' H

P

Fig.5. Example test sequence and weighted graph

for four bit inputs.

Fig.5. The greedy algorithm starts om anyscan cell which is ff in our case, as the choice of

initial state is not so crucial when the number of scancells in the graph is considerably high. From anygiven node the algorithm chooses the least weightededge leading to an undiscovered ip-op. The alseries in this case is --f-f-ff Thecomplexity of the algorithm is

(n), as for each

node all its incident edges are considered.It is important to note that this phase of

ordering is done when necessary only, as stated instep 2 of the algorithm description that the group of

test vectors that violates the peak power should beidentied rst. Hence, if no vector violates the peak

TABLE IVTEST LENGTH NEEDED TO GET TARGET

FALT COVEAGE FOR LFSR AND BS-LFSR

Lh

D l lo

9 35 1 2 U & 1 1 1 0 7 1

3 0.53 849 O 3

TABLE V

EXPEIMENTAL ESLTS OF A VEGE- ANDPEAK-POWER EDCTION OBTAINED BY

SING THE PROPOSED TECHNIQES

B w C L ode.rng WS A F WSA! lp WSAk

} 5 5 J 5 2 2

192

5723

V. EXPEIMENTAL ESLTS

The experiments was performed on full-scanISCAS89 benchmark circuits, here we using the S27sequential we using. This benchmark circuit has fourip-ops with four inputs In the rst set of

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experiments, the BS-LFSR is evaluated regarding thelength of the test sequence needed to achieve certainfault coverage with and without the scan-chainordering algoritm.

Table IV shows the results for a set of tenbenchmark circuits. The columns labeled

, m,and PI

refer to the sizes of the LFSR, the number of ipops in the scan chain, and the number of primayinputs of the CT, respectively.

The column labeled indicates thepercentage of redundant faults in the CT, and faultcoverage (FC) indicates the target fault coveragewhere redundant faults are included. The last fourcolumns show the test length needed by adeterministic test (i.e., the optimal test vector set isstored in a ROM), a conventional LFS a BS-LFSRwith no scan-chain ordering, and the BS-LFSR withscan-chain ordering, respectively.

TABLE VICOMPAISON WITH ESLTS OBTAINED IN

[10]

CRu i IS] fpros h

T %Wv Fe 406 50 2 I 7 20 9 [8 1 7 3 . 9

s? . B 6 AVG 4 4 S

The results in Table IV show that the BSLFSR needs a shorer test length than a conventionalLFSR for many circuits even without using the scanchain- ordering algorithm. It also shows that using

the scan-chain ordering algorithm with BS-LFSR willshorten the required test length.

TABLE VIICOMPAISON OF PEAK-POWER EDCTIONS

WITH ESLTS IN [14]

rc Rsu rpd Metodk Wpvg %

S78 9

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Pattern generation and FT techniques, in Froc. Int. Test Conj,2004, pp. 355364.[6] J. Sena, K. Butler, d L. Whetsel, "A analysis of power

reduction techniques in scan testing, in Froc. int T est Conj,2001 , pp. 670677 .[7] V Dabhholkar, S. Chakravarty, T Pomeranz, and S. M. Reddy,"Techniques for minimizing power dissipation in scan and

combinational circuits during test applications, iEEE Trns.Comput.-Aded Desgn Integr. Crcuts Syst., vol. 17, no. 12, pp.13251333, Dec. 1998.[8] Y. Bonhomme, P. Girard, C. Laundrault, and S.

Pravossoudovitch, "Power driven chaining of ip-ops in scachecues, n Pro. Int. Tst Ca,Oct. 2002, pp. 796803.[9] K. V Reddy and S. Chattopadyay, "A ecientalgorithm to reduce test power consumption by scan cell and scan

vector reordering, in Froc.IEEE 1st Ind Annu. Conj INDICON, Dec. 2004, pp. 373376.

[10 ] S.Wang d S. Gupta, "LT-RTPG: A new test-per-scanBST TPG for low switching activity, iEEE Trns. Comput.Aded Des Integr. CrcutsSyst., vol. 25, no. 8, pp. 156515 74, Aug. 2006.[1 1] N. Nicolici and B. A-Hashimi, "Multiple scan chains for

power minimization during test application in sequential circuits,IEEE Trns.Comput., vol. 51, no. 6, pp. 721734, Jun. 2002.

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