10.1.1.78.1225

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Parallel Fault Backtracing for Calculation of Fault Coverage

Raimund Ubar Sergei Devadze Jaan Raik Artur Jutman Tallinn University of Technology, Estonia

{raiub, serega, jaan, artur}@pld.ttu.ee

Abstract

An improved method for calculation of faultcoverage with parallel fault backtracing incombinational circuits is proposed. The method isbased on structurally synthesized BDDs (SSBDD)which represent gate-level circuits at higher, macrolevel where macros represent subnetworks of gates. Atopological analysis is carried out to generate anefficient model for backtracing of faults to minimize therepeated calculations because of the reconvergentfanouts. The algorithmis equivalent to exact criticalpath tracing. Because of the parallelism and higherabstraction level modeling the speed of analysis wasconsiderably increased. Experimental data show thatthe speed-up of the new method is considerablecompared to the previous similar approach. The speedof the fault analysis in several times outperforms the

speed of the current state-of-the-art commercial faultsimulators.

1. Introduction

Fault simulation is a widely used procedure in thedigital circuit design flow. Test generation, faultdiagnosis, test set compaction serve as examples of application of fault-free/fault simulators. Acceleratingfault simulation would improve all the above-mentioned applications.

Parallel pattern single fault propagation (PPSFP)[1] has been widely used in combinational circuit fault

simulation. Many proposed fault simulatorsincorporate PPSFP with other sophisticated techniquessuch as test detect [2], critical path tracing [3,4], stemregion [5] and dominator concept [4,6]. Thesetechniques have reduced further the simulation time.

Although the concepts of dominators and stemregions achieve substantial speed up in faultsimulation, there are still two shortcomings [7]: someregions are repeatedly simulated [1,4], and inefficiencyfor circuits with high depth [2,5]. Further improvementwas reached in [7] where the key idea was to simulate

the circuit in the forward levelized order and to pruneoff unnecessary higher level gates in the early stages.

Another group of methods like deductive [8],concurrent [9] and differential fault simulation [10] arebased on logic reasoning rather than simulation.

Deductive fault simulation [8] can be faster thanparallel fault simulation as their complexities areO(n2)and O(n3), respectively [11], where n is the number of logic gates in a circuit. There is no direct comparisonbetween the deductive and concurrent fault simulationtechniques, however, it is suspected that the latter isfaster than the former because concurrent faultsimulation only deals with the “active” parts of thecircuit that are affected by faults [12]. Differential faultsimulation [10] combines the merits of concurrent faultsimulation and single fault propagation techniques, andwas shown to be up to twelve times faster thanconcurrent fault simulation and PPSFP.

The fault analysis methods based on reasoning(deductive, concurrent and differential simulation) arevery powerful since they collect all the detectablefaults by a single run of the test pattern. What theycannot do is to produce reasoning for many testpatterns in parallel.

The Critical Path Tracing (CPT) consists of simulating the fault-free circuit and using thecomputed signal values for backtracing all sensitizedpaths from primary outputs to primary inputs, todetermine the detected faults. The trace continues untilthe paths become non-sensitive or end at networkprimary inputs. Faults on the sensitive (critical) paths

are detected by the test. CPT is also based onreasoning, and can process by a single simulation runall the faults, however it works exactly only in thefanout free circuits. A modified critical path tracingtechnique that is linear time, exact, and complete isproposed in [13]. However, the rule based strategydoes not allow simultaneous parallel analysis of manypatterns. Parallel critical path tracing in fanout freeregions combined with parallel simulation of stemfaults was investigated in [14]. In [15] the concept of parallel critical path tracing was generalized for usingit beyond the fanout free regions.

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Compared to [15] where the topological model forbacktracing of faults was created for all the outputsseparately as a set of submodels, in this paper, a joint

topological model is created for the whole circuit toavoid unneccessary repetition of the same calculationprocedures. To achieve high simulation speed, thenetwork of macros rather than gates is used. To make itpossible to rise from the lower gate level to the highermacro level, the macros are modelled by structurallysynthesized BDDs [16].

The organization of the paper is as follows. InSection 2, a method is proposed for parallel criticalpath tracing fault simulation beyond reconvergingfanout regions, Section 3 explains the topological pre-analysis of the circuit needed for building thesimulation model, experimental results are discussed inSection 4, and finally, Section 5 summarizes the paper.

2. Critical path tracing in a reconvergingfanout region

The parallel gate-level critical path tracing insidethe fanout free regions (FFR) is straightforward. Let ushave an arbitrary macro with a Boolean function

y=F(x1, …, xi, x j, … xn).

If a stuck-at fault is detected at the output y of themacro, then for every input the fault on it is alsodetected iff

1=∂∂

jxy .

The Boolean derivative is a Boolean formula thatcan be calculated in parallel for many test patterns. Inorder to extend the parallel critical path tracing methodbeyond the fan-out free regions we use the concept of partial Boolean differentials [17].

1 i

j n

f 1( ,X1)

f i( ,Xi) F

X1

Xi

Fig.1. Reconvergent FFR in a circuit

Let us have a converging gate (or macro) F of theconverging fanout region depicted in Fig.1, andrepresented by a Boolean function

y=F(x1, …, xi, x j, … xn).

Assume that the input variables x1,…,xi of the gate F are connected to the fanout stem x via macro levelnetwork represented by functions

x1 =f 1(x,X1), …, xi =f i (x,Xi).

HereXi are subsets of variables.

The function of the full convergent fanout regionwith a common fanout stemxand outputy in Fig.1 canbe represented now as a composite Boolean function

y=F(f 1(x,X1), …, f i(x,Xi),x j,… xn). (1)

Consider the full Boolean differential [17] of thegate or subcircuitF

))(),...,(),(),...,(( 11

nn j j

ii

dxxdxxdxxdxxFydFdy

⊕⊕⊕⊕⊕==

(2)

Here, by dxwe denote the change of the value of x because of the influence of a fault at x. According tothe interpretation of dy [17], dy =1 if some erroneouschange of the values of arguments of the function (1)causes the change of the value of y, otherwisedy=0.

In the following we show that the dependency of the output variable y of a reconverging FFR on thefanout stem x can be represented by a Booleandifferential equation which in its turn can betransformed to a very efficient exact procedure forcritical path tracing beyond the convergent FFRs.

Xz

Fz

Fy

1

z

Xy

Fig.2. Nested reconvergencies in a circuit

Theorem 1: If a stuck-at fault is detected by a testpattern at the output y of a subcircuit represented by aBoolean function y =F(x1, …, xi, x j,… xn), then thefault at the fanout stemx which converges in y at theinputsx1, …, xi, is also detected iff

1),...,),(),...,(( 11 =

∂∂⊕

∂∂⊕⊕=

∂∂ n j

ii xx

xxx

xxxFy

xy (3)

The proof of Theorem 1 is given in [15].

From the formula (3), a method results forgeneralizing the parallel exact critical path tracingbeyond the fan-out free regions. All the calculations in(4) can be carried out in parallel because they areBoolean operations.

Consider now a reconverging fanout circuit in Fig.2represented by a composite function y = Fy(x,z,Xy)

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wherez=Fz(x,Xz), whereasXy andXzare the subsets of variables that are not depending onx.

Theorem 2. If a stuck-at fault is detected by a testpattern on the output y of a subcircuit with two nestedreconvergencies,y=Fy(x1,z,Xy) andz=Fz(x,Xz), whereXy andXz are not depending onx, then the fault at thecommon reconverging fanout stem is also detected iff

),,( 11 yzxyx XFdz

xxFyyd ⊕

∂

∂⊕⊕= =1. (4)

The proof of Theorem 1 is given in [15].

The formula (4) can be used for calculating theinfluence of the fault at the common fanout stemx onthe output y of the converging fanout region byconsecutive calculating partial Boolean differentials,

first dxFz, and thendxy.It is easy to see that the result of Theorem 2 can beiteratively generalized for an arbitrary configuration of nested reconvergencies. On the other hand, accordingto Theorem 1, the dependencies between fanout stemsand fanout region outputs (reconverging nodes) can berepresented by full Boolean differentials and thereaftertransformed into fast computable critical path tracingprocedures.

3. Generation of the model for fault tracing

The proposed exact parallel path tracing fault analysis

is carried out in the following sessions:• topological pre-analysis of the circuit to createa model for fault tracing along the criticalpaths and subcircuits;

• parallel simulation of a given set of testpatterns to calculate the values of all variablesof the circuit;

• parallel fault backtracing on the topologicalmodel created during the first session.

The topological pre-analysis to create a model forfault backtracing is carried out only once to serve allthe next sessions of the procedure.

Compared to the previous method [15] where the

topological model for backtracing of faults was createdfor all the outputs separately as a disjoint set of submodels, in this paper, a joint topological model iscreated for the whole circuit to avoid unneccessaryrepetition of the same calculation procedures duringthe second and third sessions of the fault analysis.

The topological analysis of the circuit consists of two procedures:

• creation of the Reonvergency Graph (RG) of the circuit, and

• creation of the calculation model of the circuit.

4.1. Reconvergency graph

The first procedure of the topological analysis iscarried out in the direction from primary inputs to the

primary outputs of the circuit By this procedure, all thefanout stems and all the converging nodes of the circuitwill be found.

As the result of the procedure, a graphG =(N,Γ ) iscreated which represents a sceleton of the circuit. Thegraph consists of the nodes of the circuit, whichcorrespond to fan-out stems, reconvergent fan-in gateoutputs, and primary outputs. LetN be the set of nodes

inG, andΓ the one-to-one mapping inN, where

• Γ (n) ⊂ N is a set of successor nodes of the

noden∈ N,

• Γ -1(n)⊂ N is a set of predecessors of the node

n∈ N,• Γ -1(ni) ⊂ N is a predecessor node connected

to the input i of the noden∈ N,

• Γ *(n)⊂ N is a transitive closure of Γ (n), and

• Γ *-1(n)⊂ N is a transitive closure of Γ -1(n).

The nodes n∈ N of the graph belong to the followingsubsets:

N =FO∪FI ∪OUT,

whereFO is the set of all fan-out stems, FI is the set of all reconvergent internal fan-in gate outputs, andOUT is the set of all primary outputs of the circuit. Denote

by RO ⊆ FO the subset of reconvergent fan-out nodes

and by RI ⊆ FI ∪OUT the subset of reconvergent fan-in nodes.

To each reconvergent node x ∈ RO we refer the

ordered set of nodes RI(x) ⊆ RI , so that for eachy∈ RI(x) there exist at least two different converging pathsfromx toy. The ordering of nodes inRI(x) =(y1,…, yi, y j, …,yk) is determined by transitive closure: the node

yi is ordered beforey j iff y j ∈ Γ *(yi).

1

2

H

3

4

G C

B

D

A

E5

1

1

1

1

1

2

3

Fig.3. Reconvergency graph of a circuit

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Example 1. Consider in Fig. 3 a reconvergencygraph of a circuit which represents a topologicalskeleton of a circuit with nodes belonging to the

subsets in the following way: FO ={1,2,3,4.5,G}, FI ={H,G}, and OUT ={A,B,C,D,E}. The convergency isrepresented by the subsets: RO = {1,2,3,4}, RI ={H,G,B,C,D}, RI(1) =(H,G,B,C,D),RI(2) =(G,B,C,D),RI(3) =(B,C), RI(4) =(C,D). The procedure of pathtracing in direction from inputs to outputs with creatingof subsetsRI(n) is illustrated in Table 1.

Table 1. Topological analysis from inputs to outputs

# n Tracing paths and

findingreconvergencies

Creation of subsets

RI(x),x∈ RO

1 H (1,2), (2,H), (1,H) H⇒ RI(1)

2 G (2,3), (3,G),(H,4), (4,G) G⇒ RI(1),G⇒ RI(2)

3 B (3,B), (G,B) B⇒ RI(1),B⇒ RI(2), B⇒ RI(3)

3 C (3,C), (G,C),(4,C)

C⇒ RI(1),C⇒ RI(2),C⇒ RI(3), C⇒ RI(4)

4 D (4,G), (G,D),(4,D)

D⇒ RI(1),D⇒ RI(2),

D⇒ RI(4)

An edge (x,y) in the reconvergency graph betweentwo neighbour nodesxandyrepresents a signal path of the circuit through gates without fanouts. The inputs of the nodes in Fig.3 which represent signal paths from

primary inputs and don’t have connections with anyfan-out stem are omitted.

During the topological analysis, all the paths in thecircuit are traced, and the found reconvergencies arefixed in the form of subsetsRI(n).

Before creating a joint topological model of thewhole circuit for fault tracing purposes the next step isto build an ordered setN* of all the nodes in the graphG. The subsetN* is built by the following procedure:

1. First, all the primary outputs n ∈ OUT areincluded into N*, and ordered in an arbitraryway.

2. Each noden from the remaining subset of nodes

FO ∪FI ⊂ N will be included intoN* as soon as

Γ (n)⊂ N* will be valid.3. The procedure is finished when all the nodes of

Nare included intoN*.

Example 2. Consider the graph in Fig.3. Accordingto the described procedure, one of the possible orderingcan be as follows: N* =(A,B,C,D,E,G,3,4,5,H,2,1).

The ordered setN* of nodes of the sceleton graph of the circuit will be the basis for creating the model forfault backtracing in the circuit according to the propsedmethod.

4.2. Creation of the calculation model

The second procedure of the topological analysis iscarried out in direction from the primary outputs to the

primary inputs of the circuit. As the result of thisprocedure, we create the topological formulas for faultbacktracing for all the nodes of N* in the fixed order.

Denote by Fxy the topological formula in a form of a Boolean expresion for calculating the derivative

∂y/∂x. Denote by Fxy =xy the Boolean expression of the

derivative ∂y/∂x along the signal path (x,y) in thecircuit.

If the two consecutive paths (x,z) and (z,y) are theonly connection fromxtoy, then according to the rulesof calculating Boolean derivatives, we get thetopological formula

Fxy =xz∧ zy. (5)

Example 3. According to (5), we can calculate in

Fig.3 the Boolean derivative∂A/∂1 by the procedure

F1A =12∧ 23∧ 3A.

At each current node y ∈ N* the formulas Fxy for

all x ∈ Γ -1(y) are created as a Boolean expressionalong the path (x,y) in the circuit.

Whenever a node x ∈ FO where RI(x) ≠ ∅ is

reached then for all y∈ RI(x) the topological formulas

Fxy are created in a form of (3) or iteratively in a form

of (4).Consider a subgraph G(x,y) of the reconvergencygraphG,consisting of the nodes

N(x,y) =Γ *(x)∩ Γ * -1(y)∪ {x,y},

wherex∈ RO, y ∈ RI(x), and N(x,y) ∩ RI(x) =∅, andthe nodey has inputs {1,2,…,i}. In this case, there areno nested reconvergencies on the paths fromxtoy, and

for calculating ∂y/∂x the formula (3) can be used.

Denote the Boolean expression for calculating∂y/∂xby fault backtracing in G(x,y) from y to x based on theformula (3) as

Fxy=Rxy(xy1, xy2, ...,xyi). (6)

The arguments xyi of the functionRxy in (6) represent

the procedures of calculating the derivatives ∂xi/∂x informula (3). If the path (x,yi) travers several nodes of G(x,y) then the component xyi in (6) will be calculatedaccording to the rule of the consecutive paths (5).

Example 4. As an example, according to (6), we

calculate in Fig.3 the Boolean derivative∂G/∂1 by thetopological formula

F1H =R1H(12∧2H1, 1H2)

which according to (3) corresponds to the expression

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))1

(),1

2

2((

12

21

1∂

∂⊕

∂

∂

∂

∂⊕⊕=

∂

∂ HH

HHFH

H ,

Consider now a subgraph G(x,yi) in G(x,y)

consisting of nodes

N(x,yi) =Γ *(x)∩ Γ * -1(yi)∪ {x,y}

where x∈ RO, y ∈ RI(x), and the node y has inputs{1,2,…,i}. Let us have an ordered subset

RI(x,yi) =N(x,yi)∩ RI(x) ≠ ∅,

and let the nodezbe the last node in the ordered subsetRI(x,yi). According to the formula (5) we can calculate

∂xi/∂x, as follows:

z

x

x

z

x

x ii

∂

∂

∂

∂=

∂

∂,

which leads to the following nested topologicalformula:

Fxy=Rxy(xy1,...,xyi-1,Fxyi) =Rxy(xy1,...,xy2, xz∧ zyi). (7)

If the subgraph G(x,z) has further reconvergencies wehave to repeat the same method and replacexz in (7) bythe corresponding formulaFxz .

Table 2. Topological analysis from outputs to inputs

# n Topological formulas

Fny, x∈ RI(n)RI(n)

1 A 3A 2 B 3B; FB

3 C 3C; FC; 4C 4 D FD; 4D; 5D 5 E 5E 6 F 3F; 4F 7 3 R3B(3B1, 3G1∧GB2);

R3C(3C1, 3G1∧GC2);

B,C

8 3 23 9 4 R4C(4G2∧GC2, 4C3);

R4D(4G2∧GD1, 4D2);

C,D

10 4 H411 H 2H1; 1H2

12 2 R2G(23∧3G1, 2H1∧H4∧4G2);

R2B(23∧3B1, R2G∧GB2);

R2C(23∧3C1, R2G∧GC2,2H1 ∧H4∧4C3);

R2D(R2G∧GD1, 2H1∧G4∧4D2);

G,B,

C,

D13 2 12

14 1 R1H(12∧2H1, 1H2);

R1G(12∧23∧3G1, F1H∧H4∧4G2);

R1B(12∧23∧3B1, R1G∧GB2);

R1C(12∧23∧3C1, F1G∧GC2,

F1H∧H4∧4C3);

R1D(F1G∧GD1, F1H∧H4∧4D2)

H,G,B,C,

D

Example 5. As an example, the procedure of

calculating ∂C/∂1 in Fig.3 can be represented in thefollowing nested form:

F1C =R1C(12∧23∧3C1, R1G∧GC2, R1H∧H4∧4C3).

During the topological analysis, all the paths in thecircuit are traced according to the ordering in N*. As

soon as a reconvergent fan-out node x ∈ RO isdetected, the corresponding formulas for faultbacktracing fromy to x through the convergent regions

for all the nodes in y ∈ RI(x) are created. The resultsof this procedure are depicted in Table 2.

The formulas in Table 2 represent the faultsimulation model for the given circuit. In Table 2, 14steps of fault backtracing are described. On the stepsST1 = (1-6,8,10,11,13) parallel Boolean derivatives

during parallel fault backtracing are calculated. On theother steps, parallel Boolean derivatives according to Theorems 1 and 2, and using the results of ST1, arecalculated.

5. Experimental results

Table 3 presents the fault simulation results for thecircuits of ISCAS’85 benchmark family (column 1) tocompare different fault simulators: exact critical pathtracing [13] (column 2), two state-of-the-artcommercial fault simulators from major CAD vendors

(columns 3, 4), previous parallel critical path tracingmethod [15] (column 5), and the proposed new method(column 6).

Table 3. Comparison with previous tools

Fault simulation time, sCircuit

[13 ] C1 C2 [15 ] New

c432 70 13.0 3.8 1.2 0.77

c499 190 3.0 2.8 2.7 1.91

c880 140 26.0 4.0 1.2 0.89

c1355 640 44.0 9.0 5.0 3.28

c1908 640 53.0 15.6 5.0 3.36

c2670 560 104.0 11.0 3.8 2.76

c3540 770 191.0 37.4 9.3 6.02

c5315 1270 246.0 28.6 6.7 4.56

c6288 4280 1159.0 139.2 134.2 72.24

c7552 1480 378.0 40.5 15.0 10.09

Average 1004 221.7 29.2 18.4 10.6

The simulation times were calculated for the sets of random 10000 patterns. The time needed for topologyanalysis included in is negligible (less than 2.6% in

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average) compared to the gain in speed which is 1.7times compared to the previous method. Compared tothe commercial tools C1 and C2, the average gain in

speed is 20.8 and 2.8 times, respectively. All theexperiments were run on a 366 MHz SUN Ultra60server using SUN Solaris 2.8 operating system exeptthe experiments for the known exact critical path faultsimulator where the data are taken from [13]. To makethe comparison with [13] as compatible as possible, theexperiments were carried out on 1.5 GHz Pentium 4with WindowsXP / MS VisualC compiler (in [13] a 2.8GHz Pentium 4 Windows XP was used).

The two last columns clearly show the gain inspeed that was achieved by optimizing the topologicalmodel by the method proposed in the paper.

6. ConclusionsA method has been proposed for macro-level

parallel exact critical path fault tracing forcombinational circuits or scan-path designs.Differently from the known critical path tracingapproaches, a method is proposed to create orderedtopological model for parallel fault backtracing. Themodel is based on the full Boolean differential, whichallows generalization of the parallel critical path faulttracing beyond the reconvergent fanout stems.Considerable increase in the speed of fault simulationwas shown compared to the two state-of-the-artcommercial fault simulators, in average 2.8 and 20.8

times, respectively.Current paper allows creation of the full fault table

for a group of test patterns with a single pass of thealgorithm.

Acknowledgements

The work has been supported by Estonian ScienceFoundation grants 5910, 7068, EC 6th framework ISTproject VERTIGO, Estonian Information TechnologyFoundation (EITSA) and Enterprise Estonia.

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