ch_4_ciletti_part1

8/2/2019 ch_4_ciletti_part1

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ISRA University Islamabad

Reference Text: “Advanced Digital Design with Verilog HDL” By

Micheal D. Ciletti

Design Flow



FPGA Design Flow Verilog RTL Coding

Verilog testbench

Verilog

model

Functional/Gatesimulation

& Verification

sdc

VerilogNetlist

ToolsDesign Stage

Logic Synthesis

ucf ngcModelsim SE Verification

Text Editor

Emacs, Nedit, Vi

Verilog Design

Physical Layout

Xilinx ISEPyhsical Design &

Xilinx ISE ‐ XST

Synplify Pro

Synthesis

Device Configuration

par

Xilinx ImpactImplementation

bit

Demonstration Demonstration of Example of conditional Op project

on FPGA xc3s1500

Demonstration o using veriwe

Demonstration of using Xilinx ISE for synthesis and

.

Use of ucf File in the FPGA design Flow



User Constraint File User Constraint File specifies the connection of the

ports of

top

‐level

verilog module

the pin numbers of a particular FPGA.

Comment : #

Format :

NET “module_port<<index>>” LOC = “pin_number” ;

Example:

NET “LED<0>”

LOC

= “Y4”;

NET "out<0>" LOC = "U12";

Introductory Example: Half Adder



Primitives

The output

port

of

a primitive

must

be

first

in

the

list

of

por s. e ns ance name o a pr m ve s op ona .

3‐Input Nand



Design Encapsulation

Structural Models



Language Rules

Nested Modules

Use nested module instantiations to create a top‐

own es gn erarc y.



Nested (Cont.)

The ports of a module may be listed in any order.The

instance

name

of

a

module

is

required.

STRUCTURAL CONNECTIVITY

TIP: Use nets to establish structural connectivity.

An undeclared identifier is treated by default as a

wire.



Port Connection By Name

‐

Comparator (Assignment)



Logic System

The logic value x denotes an unknown (ambiguous) value.The logic

value

z

denotes

a

high

impedance.

Drivers The value on a wire with multiple drivers in contention

may be x



Test Methodology

To systematically verify the functionality of a model.

Approaches:

Simu ation an /or orma veri ication Simu ation:

(1) detect syntax violations in source code

2 s mu ate e av or

(3) monitor results

Example: Testbench



Behaviors for Abstract Models

Signal Generators



Event‐Driven Simulation

Testbench template



Representation of Numbers

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